Abstract: A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.

Abstract: A cryptographic processing device, comprising: a storage unit; initial setting unit for setting a value to be stored in the storage unit; Montgomery modular multiplication operation unit for performing a Montgomery modular multiplication operation plural times for a value set by the initial setting unit; and fault attack detection unit for determining whether or not a fault attack occurred for each of at least some parts of the Montgomery modular multiplication operations performed plural times.

Abstract: A semiconductor integrated circuit includes a cascode circuit having a transistor, a detector circuit and a bias generator circuit. A bias is applied to a substrate of the transistor. The detector circuit generates a signal related to a threshold voltage of the transistor. The bias generator circuit generates the bias based on the signal generated by the detector circuit.

Abstract: A data transfer apparatus in which, in a failure state such that an error packet is received at a reception end, the error packet is returned and is recorded in the transmission end, the error packet is analyzed and an error bit is identified at the transmission end, and data transmission/reception units are initialized and restarted in order to recover from the failure state.

Abstract: In one embodiment, there is provided a method for a computer aiding a design of a power supply that includes extracting data of one of a plurality of power supplies of an apparatus from product data about the apparatus, extracting data of a power supply system from power supply system data, the one of the plurality power supplies system is not allocated to any of the plurality of power supplies of the apparatus and associating the extracted data of the power supply with the extracted data of the power supply system in power supply allocation result data.

Abstract: An information processing apparatus including: a test program 2 that acquires a first voltage value which is a voltage value at which a target apparatus operates, allows the target apparatus to operate at the first voltage value, and determines an operating state of the target apparatus; a voltage change controller 12 that changes, in the case where a result of the determination is abnormal state, a voltage value difference which is a difference between a voltage value at the next stage and the first voltage value or a time difference so as to reduce the change rate obtained by dividing the voltage value difference by the time difference and outputs, when a time obtained by adding the time difference to the current time has come, a second voltage value obtained by adding or subtracting to/from the first voltage value to the test program 2 as the first voltage value.

Abstract: The mobile terminal apparatus of the present invention includes a housing having an opening section in which an accommodated object is fitted; a lid covering the opening section, the lid having a protrusion which surrounds the opening section and shields the accommodated object from water, on a surface facing the accommodated object; and a cover covering the lid, the cover being attached to the housing to press the lid onto the housing. When the cover is attached to the housing, the protrusion of the lid surrounds the opening section and is pressed onto the housing by the cover, so that the accommodated object can be reliably shielded from water.

Abstract: A patch application method restores a file not to be authorized to change by applying a patch to an original state after applying the patch. A patch application program applies a patch to a part of patch application target files in a system extracts information about the target files from a patch, copies and stores the files as patch pseudo application files, applies the patch to the pseudo files, compares the target files with the pseudo files to which the patch has been applied and obtains a difference, selects a file not to be authorized to change by the patch from among the target files based on the difference, copies and stores the files as post-application change files, applies the patch to the target files, and replaces the files prevented from being changed in the target files changed by the patch application with the post-application change files.

Abstract: A disclosed memory circuit includes first and second latch circuits, each writing a write data at a timing of a clock signal and retaining the write data, the write data having been input in each of the first and second latch circuits, a data input circuit supplying the write data to each of the first and second latch circuits when a write enable signal indicates a state allowing the write data to be written, a write back circuit supplying the write data retained in the second latch circuit to the first latch circuit when the write enable signal indicates a state preventing the write data from being written, wherein a robustness against noise in the second latch circuit is more improved than that in the first latch circuit.

Abstract: The resin layer formation method comprises the step of forming on a substrate 10 a resin layer 34 for containing a substance for decreasing the thermal expansion coefficient to thereby forming a resin layer 34 having said substance localized in the side thereof nearer to the substrate 10; and the step of cutting the surface of the resin layer 34 with a cutting tool 40 to planarize the surface of the resin layer 34. The resin layer 34 as said substance for decreasing the thermal expansion coefficient localized in the side thereof nearer to the substrate 10, and the surface of the resin layer 34 is cut to planarize the surface of the resin layer 34, whereby the extreme abrasion and breakage of the cutting tool 40 by said substance for decreasing the thermal expansion coefficient can be prevented.

Abstract: An IP-data transmitting apparatus performs an error correction coding by classifying data into a layer indicative of the priority order of the data based on importance and vulnerability of information included in the data, and combining a plurality of data components into combination patterns. The number of the combination patterns is specified with respect to each layer with predetermined priority order.

Abstract: A signal processing device includes: a wiring unit including a plurality of signal input terminals, wirings extending from the signal input terminals, and a wiring concentration section on which the wirings are concentrated; a plurality of electronic circuit units, each including a device that outputs a signal, an output control section that controls a timing at which the device outputs the signal, and a signal output terminal coupled to the signal input terminal; and a control unit that supplies a reference timing signal to the plurality of electronic circuit units, wherein each of the output control section controls a timing at which the signal is output based on the reference timing signal and phase difference information indicative of a phase difference between the signal and the reference timing signal.

Abstract: An objective function can be mathematically approximated using a prescribed number of sample sets of design parameters and sets of a plurality of objective functions computed corresponding to them. A logical expression indicating a relation between or among arbitrary two or three objective functions of the plurality of mathematically approximated objective functions is computed as an inter-objective-function logical expression and a region that the arbitrary objective function values can take is displayed as a feasible region in an objective space corresponding to the arbitrary objective functions. Furthermore, a point or area in a design space corresponding to arbitrary design parameters corresponding to a point or area specified by a user in the displayed feasible region is displayed.

Abstract: A network design device includes a bypass number setting unit setting the number of bypass node; a loss calculating unit calculating a reference loss; a graph generating unit generating a graph having a variation value obtained based on a difference between a transmission loss of a link coupling nodes to each other and the reference loss; a path detecting unit detecting a minimum-variation-path in which sum of each variation value from a start point to an end point of the graph is minimum; and a comparing unit comparing a calculation OSNR and a reference OSNR, the calculation OSNR being obtained by a calculation from a start point to an end point assuming that an optical amplifier is located on a node other than a bypass node on the minimum-variation-path, wherein the bypass number setting unit changes the number of bypass node based on a result of the comparing unit.

Abstract: As a first slot transmitting notification from an electronic device to a host device, a second slot transmitting a coupling request and a third slot transmitting notification except the coupling request are provided, and whether or not to provide the second slot may be controlled. Accordingly, it makes it possible to control a period when the second slot is provided, namely a period when the coupling request is performed, prevent the host device and the electronic device from being coupled erroneously by the unintended coupling request, and couple the host device being a communication object and the electronic device appropriately.

Abstract: An apparatus includes a context information extracting part that monitors a state of the apparatus and extracts context information indicative of the state; a note information saving part that saves note information in association with context information when the note information for displaying is registered; a context information similarity evaluating part that determines, for each piece of the note information, similarity between the context information extracted by the context information extracting part at a certain point in time and context information which is associated with note information saved by the note information saving part; and a note information display part that displays the note information saved in the note information saving part in a display mode in accordance with the determined similarity of the note information.

Abstract: A cache controller that writes data to a cache memory, includes a first buffer unit that retains data flowing in via an external bus, a second buffer unit that retrieves a piece of the data to be written to the cache memory, and a write controlling unit that controls writing of the piece of the data retrieved by the second buffer unit to the cache memory.

Abstract: An image processing apparatus includes a level-value-limit smoothed-image creating unit, a level-value combining unit, and a smoothed-image creating unit. The level-value-limit smoothed-image creating unit calculates, from the pixels in a received input image within a filter size of the low-pass filters each having different level value ranges, an average value of the pixels in the level value ranges, and creates level-value-limit smoothed images. The level-value combining unit creates a level-value combined image by selecting and combining one or more of the level-value-limit smoothed images. The smoothed-image creating unit determines, based on image information that is different from image information used by the level-value-limit smoothed-image creating unit, a combining ratio of the input image to the level-value combined image and creates a smoothed image by combining the input image and the level-value combined image using the determined combining ratio.

Abstract: An automatic frequency monitoring circuit automatically monitors a frequency of a clock related to an operation of a device to be monitored. In the automatic frequency monitoring circuit, a frequency detecting unit detects, upon detecting a predetermined momentum, the frequencies of a monitoring target clock during a predetermined time for a predetermined number of times and treats as a detection frequency of the monitoring target clock, an average of the frequencies that are detected for the predetermined number of times. A frequency monitoring unit monitors, upon the frequency detecting unit detecting the detection frequency of the monitoring target clock, whether the frequency of the monitoring target clock during the predetermined time is within a predetermined fluctuation range based on the detection frequency.

Abstract: A disk array apparatus with a number of storage units aims at application of new control firmware to the storage units. The disk array apparatus includes a controlling unit controlling the storage units, which controlling unit includes a storing section storing control firmware to be applied; a monitoring section for monitoring a state of access to each storage unit to which the control firmware is to be applied; and an application instructing section instructing, on the basis of the result of the monitoring by the monitoring section, each the first storage unit to apply the first control firmware. In response to the instructing by the application instructing section, the control firmware is applied to each the storage unit.