Abstract: A bias generator comprises a first transistor and a second transistor having a control port connected to a control port of the first transistor and to an input port of the second transistor, where a second current through the second transistor is greater than a first current through the first transistor. The current through the bias generator is minimized by providing the different currents through the transistors having a similar size.

Abstract: The system includes a bounds primitive rasterizer that rasterizes a bounds primitive into a selection of primitive pixels. The selection of primitive pixels bounds a shape to be rendered to a screen. The system also includes a pixel mask generator that generates a pixel mask for the shape. The pixel mask includes mask pixels that each corresponds to one of the primitive pixels. A mask pixel is a covered pixel when the shape covers at least a threshold portion of the mask pixel and is an uncovered pixel when the shape does not cover the mask pixel. The system also includes a pixel screener configured to retain primitive pixels that correspond to covered mask pixels and to discard primitive pixels that correspond to uncovered mask pixels.

Abstract: This disclosure describes rate control techniques that can improve video encoding. In particular, the described rate control techniques exploit relationships between the number of bits encoded per frame and the number of non-zero coefficients of the video blocks after quantization. The number of number of non-zero coefficients of the video blocks after quantization is referred to as rho (?). The value of ? is generally proportional to the number of bits used in the video encoding. This disclosure utilizes a relationship between ? and a quantization parameter (QP) in order to achieve rate controlled video encoding. More specifically, this disclosure provides techniques for generating a lookup table (LUT) that maps values of ? to different QPs.

Abstract: A single-stage amplifier includes (1) first and second “gain” transistors coupled in a common source configuration, (2) first and second resistors providing self-biasing for the first and second transistors, respectively, (3) first and second current sources providing bias currents for the first and second transistors, respectively, and (4) a load impedance coupled between the drains of the first and second transistors. The amplifier may further include (5) third and fourth “compensation” transistors coupled in parallel with, and used to compensate parasitic capacitances of, the first and second transistors, respectively, and (6) third and fourth resistors providing self-biasing for the third and fourth transistors, respectively. Variable gain may be achieved by varying the bias currents for the gain transistors. A two-stage amplifier may be formed with two stages coupled in cascade, with each stage including most or all of the circuit elements of the single-stage amplifier.

Abstract: An apparatus, system, and method provide optimization of color space conversion using a joint quality metric representing differences between reference human visual representations and converted device captured image representations in a perceptual uniform color space, where the conversion includes transforming a nonstandard color space (RGB) to a perceptual standard color space (sRGB) and where the joint quality metric includes a color portion, a noise portion, and a contrast portion. An optical sensor produces a digital reference signal when capturing an image of a reference source such as a Macbeth ColorChecker color rendition chart. After white balancing and color correcting the digital reference signal, the gamma curve parameters are determined by minimizing the joint quality metric which is based on differences, within a uniform perceptual color space such as CIELAB, between the gamma curve compensated signal and the standard values for the reference source.

Abstract: A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages. The first stage includes three operand alignment units, two multiplexers, and three latches. The three operand alignment units operate on a current floating-point value, a prior floating-point value, and a prior accumulated value. A first multiplexer provides zero or the prior floating-point value to the second operand alignment unit. A second multiplexer provides zero or the prior accumulated value to the third operand alignment unit. The three latches couple to the three operand alignment units. The second stage includes a 3-operand adder to sum the operands generated by the three operand alignment units, a latch, and a post alignment unit.

Abstract: A variable inductor can be formed on an integrated circuit with a primary conductor, a secondary conductor, and a switch. The primary conductor implements an inductor and may be formed in various patterns (e.g., a spiral). The secondary conductor forms a loop in proximity to (e.g., on the outside of) the primary conductor. The switch couples in series with the secondary conductor and opens or closes the loop. The inductance of the inductor is varied by closing and opening the loop with the switch. A current source may also be coupled in series with the secondary conductor and used to control the current flow in the secondary conductor to either increase or decrease the inductance. Multiple loops may be formed to change the inductance in more than two discrete steps. The variable inductor may be used for various applications such as filters, VCOs, and impedance matching networks.

Abstract: Techniques to reduce LO leakage by controlling the amplitude of LO signal based on the level of output signal after the frequency conversion process. An LO generator receives a VCO signal and generates an LO signal having a variable amplitude and a frequency that is related to the frequency of the VCO signal. A variable gain amplifier receives a control signal and adjusts the amplitude of the LO signal based on the control signal. The variable amplitude LO signal is used for frequency upconversion (e.g., direction upconversion) of an input signal (e.g., at baseband) to obtain an output signal (e.g., at RF). The relationship between LO signal amplitude and output signal level may be defined by a particular transfer function. In general, the LO signal is set higher for higher output signal level and is reduced proportionally for lower output signal level.

Abstract: A power estimator for a Code Division Multiple Access (CDMA) receiver. A noise estimate of a received channel may be made by demodulating a received signal using an empty code or Walsh channel. The noise estimate may also be made by demodulating the Pilot signal in systems where potentially all Walsh codes are assigned to active channels. Where the channels are quadrature phase modulated, the noise estimator may take advantage of the Pilot channel configuration by demodulating only the quadrature element of the Pilot channel. The noise estimator demodulates the Pilot using signal processing stages that statistically correspond to the signal processing performed on traffic channels. The statistics of the processing performed in the noise estimate closely track the statistics of the signal processing performed on the traffic channels.

Abstract: Techniques for processing incoming signals conforming to a plurality of standards or communication formats with a single baseband receive section are disclosed. In one aspect, a plurality of analog processing components are adjusted in response to a format select signal, set according to one of a plurality of supported formats or standards. In another aspect, the operating mode of an A/D converter is tuned in response to the format select signal. In yet another aspect, the response characteristics of a jammer filter are tuned in response to the format select signal. In yet another aspect, the adjustment of the plurality of analog processing components is carried out by varying the frequency of a sample clock in response to the format select signal. Various other aspects are also presented. These aspects have the benefit of allowing a single baseband receive section to be deployed to process analog signals conforming to a plurality of communications standards or formats, in a power and area efficient manner.

Abstract: An on-chip detection circuit automatically detects when an external switch has been activated. When the device is initialized, the detection circuit measures the operating current and coverts the information into an analog voltage. The analog voltage is then processed through an on-chip analog-to-digital converter and the digitized result is stored as a reference value. To sense the open and close action of the off-chip mechanical switch, the device then takes a sample of the operating current periodically, digitizes this information and compares the sampled value to the reference value. A change in value larger than some predetermined level indicates the external switch has been activated.

Abstract: Techniques for reducing search time using known scrambling code offsets are disclosed. In one embodiment, a plurality of search results is generated by correlating a received signal with a synchronization sequence. The plurality of search results is reduced by removing any results whose offset is within a threshold of a stored offset. In another embodiment, stored offsets correspond to previously identified cells. In yet another embodiment, a searcher further correlates the received signal with a scrambling code over a search window to produce a list search result. The scrambling code may be associated with one of the cells in a neighbor list. Various other embodiments are also presented. Benefits include efficient searching which allows for improved base station selection and therefore improved performance and system capacity.

Abstract: Techniques for controlling transmit power for a data transmission sent on multiple data channels, which may be intermittently active, are described. Each data channel is monitored for activity (e.g., based on an error correction code, received signaling information, received block energy, and so on) and deemed to be dormant or not dormant (e.g., based on the amount of elapsed time since activity was last detected on the data channel). A signal quality (SIR) target may be maintained for each non-dormant data channel and updated based on the status of received data blocks for the data channel. A final SIR target, used for power control of the data transmission, may be set to the highest SIR target among the SIR targets for the non-dormant data channels. The final SIR target may also be updated directly based on the status of received data blocks for the non-dormant data channels.

Abstract: Techniques for scheduling measurements for cells in multiple (e.g., GSM and W-CDMA) wireless communication systems are described. GSM neighbor cells are categorized based on a number of states. The states are prioritized in a manner to achieve good performance. The GSM neighbor cells are thus assigned different priorities depending on their states. W-CDMA neighbor cells are prioritized relative to the states for GSM cells. All W-CDMA neighbor cells can be assigned the same state, given the same priority, and considered as “one” W-CDMA cell in the scheduling. A cell in the GSM or W-CDMA system is selected based on the priorities of the neighbor cells, and the selected cell is scheduled for measurement in the next available frame. The highest-ranking GSM or W-CDMA cell for each idle frame is thus granted use of that idle frame for measurement.

Abstract: Techniques for inter-frequency neighbor list searching are disclosed. Embodiments disclosed herein address the need for inter-frequency neighbor list searching. In one embodiment, a searcher is deployed to search a PN space with a first set of search parameters and to return search results. A subset of those results are selected, along with a previously saved search result, to form a set of PN locations for a second search. The second search is performed on a window around each of the PN locations, using a second set of search parameters. The maximum peak from the second search is saved for use in future iterations. In one embodiment, the subset is selected as the highest energy level peaks from the first search. In one embodiment, if a maximum peak is deemed to correspond to a valid base station when the position of that maximum peak is within a pre-determined time offset from a previous maximum peak.

Abstract: Interoperability between wireless communication systems, such as the IS2000-1x and IS856 systems, is facilitated by using supervision timers. A wireless communication device starts one or more supervision timers and performs an intersystem transition. When the wireless communication device returns from the transition, the supervision timers are used to estimate the duration of the transition. The wireless communication device then performs a sequence of tasks appropriate to the estimated duration.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: A method, system, and apparatus for automated electromagnetic compatibility-driven (EMC-driven) layout and floor planning of electronic devices and systems accounts for electromagnetic interactions between circuit components and addresses internal EMC issues at the outset of the design phase. Problems that may affect system performance are predicted, and a new layout optimized for reduced electromagnetic interference may be suggested, before an expensive prototyping operation is performed. Causes of such problems are also identified with better certainty than is possible from a defective prototype, resulting in a reduced design cycle.

Abstract: A system determines if a primary paging channel should be received based on an examination of a quick paging channel. A first QPCH symbol is examined (102) and the normalized pilot energy is determined (104). If the normalized pilot energy is above a first threshold (106), the symbol is demodulated and the QPCH-symbol-to-pilot-energy ratio is determined (110) and compared against another threshold (112). If the normalized pilot energy is below the first threshold, the system proceeds to the second QPCH symbol immediately. Depending on the resulting values, a second QPCH signal is examined (108), the system sleeps (114), or the system decides (116) to process the primary paging channel directly (118). If the second signal is demodulated, and if its normalized pilot energy is high enough, it also is demodulated and the ratio of the sum-of-the-combined-QPCH-symbols to the sum-of-the-combined-pilot-energies is determined (122).

Abstract: In one disclosed embodiment, a mobile unit receives an assigned reverse supplemental channel data rate, for example, as part of a supplemental channel assignment from a base station to the mobile unit in a cdma spread spectrum communication system. The mobile unit utilizes a profiling table to determine a maximum feasible reverse supplemental channel data rate corresponding to a given forward supplemental channel data rate. For example, the profiling table can be constructed by testing the mobile unit to determine what combinations of forward and reverse supplemental channel data rates and operating conditions cause the mobile unit's processor to “crash”. The mobile unit communicates data over the reverse supplemental channel at a data rate which does not exceed the maximum feasible reverse supplemental channel data rate, for example, by constructing service data units using filler to lower the communication data rate below the maximum feasible reverse supplemental channel data rate.