Patents Represented by Attorney George Sai-Halasz
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Patent number: 7563657Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.Type: GrantFiled: January 9, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventor: Jack Oon Chu
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Patent number: 7547930Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected work function. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.Type: GrantFiled: January 11, 2008Date of Patent: June 16, 2009Assignee: International Business Machines CorporationInventor: Jack Oon Chu
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Patent number: 7525161Abstract: NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.Type: GrantFiled: January 31, 2007Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Meikei Ieong, Xiao Hu Liu, Qiqing Christine Ouyang, Siddhartha Panda, Haizhou Yin
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Patent number: 7510916Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.Type: GrantFiled: January 10, 2008Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventor: Jack Oon Chu
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Patent number: 7498943Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.Type: GrantFiled: October 27, 2006Date of Patent: March 3, 2009Inventors: Ildiko Medve, George Sai-Halasz
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Patent number: 7494861Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.Type: GrantFiled: January 14, 2008Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Bruce B. Doris, Meikei Ieong, Jing Wang
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Patent number: 7413941Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.Type: GrantFiled: May 13, 2006Date of Patent: August 19, 2008Assignee: International Business Machines CorporationInventors: Ying Zhang, Bruce B. Doris, Thomas Safron Kanarsky, Meikei Ieong, Jakub Tadeusz Kedzierski
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Patent number: 7411214Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.Type: GrantFiled: February 26, 2005Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventor: Jack Oon Chu
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Patent number: 7410844Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.Type: GrantFiled: January 17, 2006Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Yujun Li, Kenneth T. Settlemyer, Jr., Jochen Beintner
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Patent number: 7389530Abstract: A portable computing device for opening a door (an electronic door opener) and a method for its use is disclosed. The computing device has a shared secret key, a standard certificate, means for communicating with the door, and a processor adapted for performing operations with shared secret keys and standard certificates. The door also possesses the same shared secret key. Under normal operation, messages encoded with the shared secret key serve to establish a right to open the door. The portable computing device's standard certificate is used to respond to occasional challenges by the door, and to generate the shared secret key. Biometric capabilities of the portable computing device add an additional layer of security in screening the identity of the user of the device. A security system for controlling access, involving a first plurality of computing devices and a second plurality of doors, and operating based on shared secret keys and occasional challenges is also disclosed.Type: GrantFiled: September 12, 2003Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Mandayam Thondanur Raghunath, Chandrasekhar Naravanaswami
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Patent number: 7388258Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.Type: GrantFiled: December 10, 2003Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Ying Zhang, Bruce B. Doris, Thomas Safron Kanarsky, Meikei Ieong, Jakub Tadeusz Kedzierski
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Patent number: 7387925Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: April 10, 2007Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
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Patent number: 7387924Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: GrantFiled: September 18, 2006Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Robert J. Miller, Erin C. Jones, Atul Ajmera
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Patent number: 7368358Abstract: A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.Type: GrantFiled: February 2, 2006Date of Patent: May 6, 2008Assignee: International Business Machines CorporationInventors: Qiqing C. Ouyang, Xiangdong Chen
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Patent number: 7358122Abstract: Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.Type: GrantFiled: February 25, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventor: Jack Oon Chu
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Patent number: 7355514Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.Type: GrantFiled: October 30, 2006Date of Patent: April 8, 2008Inventors: Ildiko Medve, George Sai-Halasz
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Patent number: 7348629Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.Type: GrantFiled: April 20, 2006Date of Patent: March 25, 2008Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Bruce B. Doris, Meikei Ieong, Jing Wang
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Patent number: 7244976Abstract: A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.Type: GrantFiled: January 25, 2005Date of Patent: July 17, 2007Assignee: International Business Machines CorporationInventors: Jin Cai, Tak Hung Ning
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Patent number: 7244958Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: June 24, 2004Date of Patent: July 17, 2007Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
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Patent number: 7183175Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.Type: GrantFiled: July 1, 2005Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Steven John Koester, Klaus Dietrich Beyer, Michael John Hargrove, Kern Rim, Kevin Kok Chan