Abstract: A method and system are disclosed for a DRAM having a single stage sensing architecture. In this architecture during a Read operation, in any datapath connecting a memory cell to a data I/O, there is one and only one sense amplifier. This sensing and latching scheme allows for the fast execution Read, Write, Write-back, and Refresh operation. Depending on the embodiment, Read and Write-back operations are executed in one, or two, cycles. Multiplexing of arrays and bit-linens results in efficient use of chip area.

Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.

Abstract: A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.

Abstract: A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.