Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: A device for phase alignment between a data signal and a main clock signal, characterized by the fact that, from a main clock signal, it has some means of generation of clock signals which are phase-shifted with respect to one another by a fraction of a period of said main clock signal, some means 10 of dividing the input data signal by sampling of said signal by said clock signals in order to obtain data signals with a length equal to said fraction of a period of said main clock signal, observation window 14 of said sampled data bits, said window 14 having a length equal to a data bit of the entering signal, a set of pipelines 16 for parallel processing using an algorithm of the signals transmitted by the observation window in view of retrieving data signals, and device 18, 19 for drift compensation.

Abstract: A Reed-Solomon encoding device is provided that can handle multiple RS (Reed-Solomon) codes using different field generation polynomials. The encoding device uses a first Galois field transformation that transforms source data into a specified Galois field on the basis of a first Galois field transformation parameter. The transformed source data is received by an encoder that performs encoding processing using a selected multiplication coefficient set. A second Galois field transformation is used for performing an inverse transform of the encoded data on the basis of a second Galois field transformation parameter. A parameter output is used for outputting the first Galois field transformation parameter, the second Galois field transformation parameter, and the selected multiplication coefficient set. The parameter output generator is operable to be loaded with transformation parameters and multiplication coefficients selected from a plurality of transformation parameters and multiplication coefficients.

Abstract: A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. A plurality of algorithm modules is combined with a framework to form the software program. Each of the plurality of algorithm modules has a memory interface which responds to a memory allocation inquiry with memory usage requirements of an instance of the algorithm module. The software program is then loaded on a hardware platform and executed. During execution, the framework sends a query to the memory interface of each of the plurality of algorithm modules to request memory usage requirements for each instance of each of the plurality of algorithm modules.

Abstract: A data processing system (1300) is provided with a digital signal processor (DSP) (1301) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D1, .D2) connected to dual memory ports (T1, T2) in a level one data cache memory controller (1720a). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.

Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width (1110-1115) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats (1100, 1102) are combined with non-operational instructions (NOP, NOP—16) to form a large number of combination instructions that match any instruction length format.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A trace FIFO (800) is provided for tracing a sequence of instruction addresses to assist with software or hardware debugging. In order to conserve space, only the addresses of an instruction just before (M+K, P+Q) and just after (P, R) a discontinuity are stored in the trace FIFO. A sequence of instruction lengths (SEC13LPC) is also stored in the trace FIFO so that the sequence of instruction addresses can be reconstructed by interpolating between two discontinuity points (P to P+Q).

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. Two sets of interrupt vectors are maintained. Interrupts vectors pertaining to interrupts originated by one set of interrupt sources (820, 821, 822) are stored in a DSP interrupt vector table (850) located in a memory circuit 801 that is private to the DSP. Interrupt vectors pertaining to interrupts originated by a host processor (810) are stored in a Host interrupt vector table (851) located in a dual ported communication memory circuit (802). The DSP executes interrupt service routines to service all of the interrupts, but the host can change the interrupt vectors for host initiated interrupts.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. An instruction (1003) is decoded and accesses a data item in accordance with an address field (1003a). Another instruction (1002) is decoded and accesses a data item in accordance with an address field (1002a); but in a different manner due to an instruction qualifier (1002b). The instruction qualifier is executed in an implicitly parallel manner with the qualified instruction (1002).

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.

Abstract: An integrated code development tool, comprising of an editor, a project management and build system, a debugger, a profiler, and a graphical data visualization system. The editor is operable to provide a source code view which is simultaneously capable of integrating with said debugger to provide for stepping through code and setting breakpoints, and integrating with the output of said build system to display source code interleaved with corresponding assembler code created by said build system.

Abstract: A digital system is provided with an Analog to Digital converter (ADC) that has a configuration that allows a programmable number of Auto conversions to occur on two separate and independent, but cascadeable, sequencers (or state machines). For each conversion state, the sequencer/s can be programmed to arbitrarily select any one of a set of muxed analog input channels. In addition, each conversion state has a unique result register in which the converted value is placed at completion of conversion. This ADC control system gives the capability to set up various forms of input signal sampling strategies. For example, one such strategy samples and converts the same channel multiple times allowing an over-sampling algorithm to be easily performed. By over sampling, increased resolution over traditional single sampled conversion systems can be obtained by suitable processing of the over-sampled results.

Abstract: A zero anticipation mechanism for an arithmetic unit 42 of a processing engine includes an array of cells 420, 430 interconnected to produce an ordered sequence of intermediate anticipation signals. The array of cells includes cells connected to receive intermediate result signals from the arithmetic unit, cells for forwarding an intermediate anticipation signal supplied thereto, and cells for generating a combination of first intermediate anticipation signals and second intermediate anticipation signals supplied thereto. The zero anticipation mechanism implements a zero look-ahead mechanism which can predict a zero result 479 prior to the arithmetic unit completing an arithmetic operation.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE [0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. A FIFO is provided on a peripheral device to reduce data transfer access time. When the FIFO is almost empty, a FIFO management state machine requests a DMA transfer by asserting the nDMA_REQ signal on the interconnect bus, thus transitioning from idle state 2300 to transfer state 2310 along arc 2301. The DMA controller transfers several data words until the FIFO becomes full, as indicated by word_cpt=FIFO_size.

Abstract: An on-screen display with variable resolution capability permits respective parts of a screen to be processed according to their respective resolution requirements. For any active window in the on-screen display, the data format used in memory to represent the pixels of that window can be determined, thereby permitting the window resolution to vary from window to window.

Abstract: A data processing system having a central processing unit (CPU) with address generation circuitry for accessing a circular buffer region in a non-aligned manner is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory ports. A data transfer address for each load/store instruction is formed by fetching the instruction (600), decoding the instruction (610) to determine instruction type, transfer data size, addressing mode and scaling selection.

Abstract: A buried-channel PMOS device is fabricated simultaneously with a surface-channel device if the gate is doped N-type while the NMOS gates are doped and the P+ source/drain doping is blocked from the “high” P-channel device. In the normal process the “high” PMOS is not fully self-aligned. However, when the PMOS process includes a lightly-doped drain (PLDD), the LDD doping is self-aligned.

Abstract: A processor core is provided that is a programmable digital signal processor (DSP). The microprocessor is operable to execute a sequence of instructions obtained from an instruction bus and has program counter circuitry for providing a first instruction address to the instruction bus. An instruction buffer is operable to hold at least a first instruction of the sequence of instructions obtained from the instruction bus. Breakpoint event generation circuitry is connected to the instruction bus and is operable to detect a designated mark instruction and a designated chain instruction in the sequence of instructions. Tag circuitry is associated with the instruction buffer and is operable to hold a mark tag and a chain tag, and is further operable to be set in response to the breakpoint event circuitry. An instruction execution pipeline is connected to receive the sequence of instructions from the instruction buffer register along with respective mark tags and chain tags from the tag circuitry.