Abstract: The objective of the invention is to provide a DSP that can perform hold testing, which evaluates the halt state of the DSP core, during DSP core self-testing. DSP circuit 2 has input scheduler 8 that outputs restart signals to halt terminal HALT, which controls operation halt/restart for the of DSP core 4, when a fixed time has elapsed after operation of DSP core 4 has halted during hold testing, so the stopped DSP core 4 can be restarted. Thus, the internal state of DSP core 4 when operation restarts, can be recognized by the DSP core 4 itself, so it will be possible to implement hold testing that evaluates whether or not the DSP core 4 has correctly halted operation.

Abstract: A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming 200 a gate oxide layer on a semiconductor substrate, forming 210 a dummy gate on the substrate, removing 260 the dummy gate after further processing and depositing 270 a lower metallic gate material on said gate oxide; treating 280 the semiconductor device with a reducing gas immediately after deposition of the lower metallic gate material, and depositing 290 an upper gate metal over the lower gate material.

Abstract: Circuitry for identifying digital data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal is provided. The circuitry includes a means (30) for extracting data from each header signal, which data is representative of a corresponding useful signal, a means for storing reference data in a memory, at addresses each corresponding to a packet type, and a means for comparing the data extracted from each header signal with said reference data stored in memory, and for the delivery, to a data processing unit (32,34), of an address signal indicating the nature of the corresponding packet. The data storage means and the comparison means preferably employ an associative memory (38) adapted to ensure the simultaneous comparison of the data extracted from each header signal with the reference data stored in memory.

Abstract: In a computer system (10) embodiment, there is included a memory (18) and circuitry (16a) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (14), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (16b, 16n, 17) using the system resource. The system further includes circuitry (20, 22, 24) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (26) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: A clock generation circuit 122 with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path 504 so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry 531 in or out of the non-overlap feedback path on signal line 504. A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit 561 or a scan latch 562 also can select the non-overlap time period.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures of transistor gate oxide. A methodology is provided that is a practical approach to full-chip crosstalk noise verification and gate oxide integrity analysis. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups. Selected signal lines are then fully simulated to determine gate oxide field strengths on transistors connected to the selected signal lines.

Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.

Abstract: An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

Abstract: Data processing apparatus 10 supporting circular buffers CB includes address storage ARx for holding a virtual buffer index and offset storage BOFxx for holding an offset address. Circular buffer management logic 802 is configured to be operable to apply a modifier to a virtual buffer index held in the address storage to derive a modified virtual buffer index and to apply a buffer offset held in the offset storage to the modified virtual buffer index to derive a physical address for addressing a circular buffer. By employing virtual addressing to a buffer index for a circular buffer management, it is possible to make efficient use of memory resources. One or more circular buffers can be located contiguously with respect to each other and/or other data in memory, avoiding fragmentation of the memory. The buffer index forms a pointer for the circular buffer.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A method is provided for extracting parasitic data in a hierarchical manner from a trial layout of the integrated circuit. Intracellular parasitic data representative each cell type used in the integrated circuit is extracted only once, regardless of the number of times the cell is instantiated in the integrated circuit. For each instance of each cell, a portion of intercell signal lines that are routed over that instance of the cell are cut out in cookie cutter fashion by specifying an area in the trial layout corresponding to the instance of the cell such that the portion of intercell signal lines within the area can be processed apart from the remaining portion of the intercell signal lines.

Abstract: The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at least a portion of the collector region. The method further comprises forming a diffusion blocking layer over the base region, and forming an emitter polysilicon region over the diffusion blocking layer. The diffusion blocking layer reduces an amount of diffusion from the emitter polysilicon region into the base region, thereby allowing improved process control and emitter/base doping profile, leading to improved transistor performance. In addition, the present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region.

Abstract: An integrated circuit is provided with a local electrostatic discharge (ESD) protection circuitry (120) associated with each signal pad. The integrated circuit has internal circuitry (100) that operates at a low supply voltage, but at least some of the interface signals impressed on the signal pads operate at a high supply voltage. The local ESD protection circuitry associated with each signal pad comprises only a pair of diodes connected respectively to the ground reference bus and a high voltage supply bus. A few shared clamp circuits (222) are connected to the voltage buses and clamp any ESD voltage surge that is transferred to the high voltage bus by the individual signal pad ESD protection circuits. The clamp circuits use cascoded low voltage MOS devices (P1, N1, P2) that are biased during normal operation so that electrical over-stress does not occur.

Abstract: An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.

Abstract: A data processing device uses a portion of a random access memory as an output buffer for holding a frame of PCM sample data which is being output after being processed by a processing unit within the processing device. Fine grained synchronization between a reference clock and a stream of PCM data frames is provided by transferring only a portion of selected frame of PCM sample data PCM(n+1), in response to a time difference 971. A breakpoint address is determined to delineate the portion of the selected frame that is to be transferred. A sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint register is sufficient to monitor addresses as they are provided by an address register for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task 802.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) which uses low voltage transistors (N1, N2) to provide protection to a signal pad that handles high voltage signals during normal operation of the integrated circuit. The external signal is operable at a second supply voltage that is higher than the Vdd supply voltage. The internal circuitry of the integrated circuit is comprised of MOS transistors that have gate oxide of a first thickness that has a Vox-max suitable for the Vdd supply voltage but not for the second supply voltage. The ESD protection transistors use the same gate oxide thickness as the MOS transistors used in the internal circuitry. A substrate region in the semiconductor substrate is enclosed by a highly doped region (250) so that the back-gates of the ESD protection transistors can be voltage pumped by pump circuitry (202) in order to trigger bipolar conduction of the ESD protection transistors at a lower voltage.

Abstract: A circuit 10 is provided that comprises a source resistance transistor 12 connected to a common node 14. A word line driver circuit 18 receives current if it is the word line driver selected from the VDD supply voltage through the source resistance transistor 12. The gate of source resistance transistor 12 is connected to a bond pad 22 which can be alternatively connected to the VDD supply voltage through a bond pad 24 or to ground potential through a bond pad 26. The effective threshold voltage of a transistor 18 within driver 16 can be adjusted depending upon how the gate of transistor 12 is connected. In this manner, a circuit can be adjusted to compensate for process variation or to be more optimum for a selected application by adjustment of the effective threshold voltage of selected transistors.

Abstract: An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.

Abstract: A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry 913 selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor 910 to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control 915 parses the immediate value to determine how to combine the immediate value and the index value.

Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.