Abstract: A method for designing and fabricating an integrated circuit is described. An increase or a decrease in a total propagation delay time 311 of a signal on a victim net 203 is accurately modeled using a modified decoupled simulation model 300. Victim net 203 is modeled as a distributed capacitor 320a-c that has a total value equal to Cgnd+2*K*Ccoup. A match propagation delay time which includes a variation in propagation delay caused by signal coupling from aggressor nets located adjacent to the victim net is determined by simulating a representative circuit using a coupled distributed load simulation model to accurately determine the match propagation delay time. K is determined using an equation in which K=1+(match delay−unmodified delay)/(2*R*Ccoup). R is the effective drive resistance of a buffer which drives the victim net and associated signal trace resistance.

Abstract: An operating system preferably for use with a digital signal processing target is disclosed which minimizes time and space requirements on the target DSP chip. The operating system is also configured in accordance with parameters entered by a user regarding the application being developed.

Abstract: An improved integrated circuit including decryption functions employs a method for determining if its environment has been modified, by providing a first VCXO as part of the integrated circuit, providing a second VCXO, adjusting one of the VCXOs in a first preselected manner, determining a first frequency count of the adjusted VCXO during a first preselected time interval using the other VCXO, adjusting the one of the VCXOs in a second preselected manner, determining a second frequency count of the adjusted VCXO during the first preselected time interval using the other VCXO, averaging the first and second frequency count to provide an average frequency count, adjusting the average frequency count in a predetermined manner, and comparing the adjusted average frequency count to a previously stored, determined, or provided average frequency count to determine if the environment of the integrated circuit has been modified.

Abstract: A data processing device is provided which has multiprocessors that can be configured on a cycle by cycle basis as loosely coupled or tightly coupled. Bit-stream Processing Unit (BPU) 110 executes instructions from ROM 112 and accesses data from RAM 111. Similarly, Arithmetic Unit (AU) 120 executes instructions from ROM 122 and accesses data from RAM 121. Both processor operate in parallel and exchange data by accessing RAM 121. AU 120 can receive an instruction directive from BPU 110 directing it to perform a selected sequence of instructions in a loosely coupled manner. AU 120 can also receive an instruction directive from BPU 110 directing that a portion of AU 120 operationally replace a portion of BPU 110 for the duration of one instruction which allows data to be passed directly between the processors in a tightly coupled manner.

Abstract: A transport stream parser system is provided that utilizes an intermediate buffer for containing packets after processing with an associated flag and then use a processor for further processing of packets selected by such flags.

Abstract: Apparatus for generating and displaying data on a monitor 28 such as a CRT of LCD display. The display is comprised of a plurality of images, each located at positions on the face of the monitor defined by multi-digit coordinate values in a multi-coordinate system. Units of data are stored in linear display memory 26, each such unit of data corresponding to and defining the image to be displayed at one of said positions. The apparatus includes a circuit 60 which places selected bits of said multi-digit coordinate values in a preselected order to define the address or offset in said linear display memory at which is located the corresponding unit of data.

Abstract: A data processing device uses a portion of a random access memory as an input buffer for holding a portion of a stream of data which is being processed by a processing unit within the processing device. Various break-point source tasks 801a-n determine discontinuities in the portion of data stored in the input buffer and a sorted list of the addresses of the discontinuities is maintained in breakpoint queue 800. Since the buffer is managed in a FIFO manner, a single breakpoint register 810 is sufficient to monitor addresses as they are provided by an address register 820 for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task 802.

Abstract: A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.

Abstract: A microprocessor (5) for coupling to an external read/write memory (20) having an addressable storage space. This storage space stores cacheable digital data and non-cacheable (32) digital data. The microprocessor includes a data storage circuit (62) for storing a portion of the non-cacheable data. The microprocessor further includes an address storage circuit (64) for storing an address corresponding to the portion of the non-cacheable data. Still further, the microprocessor includes a counter (72) for advancing a count from an initial value (74) toward a threshold value (76) in response to an activity over time. The counter initiates its advancing operation in response to the data storage circuit receiving the portion of the non-cacheable data. Lastly, the microprocessor includes an indicator (66) for indicating the portion of the non-cacheable data in the data storage circuit is expired in response to the count reaching a threshold.

Abstract: A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using .mu.-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Abstract: An output buffer with switching PMOS drivers (10) is disclosed. According to one embodiment, output buffer (10) includes a first output driver (62) and a second output driver (68). A first output cascode (64) coupled to the first output driver (62) protects the gate oxide of the first output driver (62) from voltage changes on the output (16). A second output cascade (66) coupled to the second output driver (68) protects the gate oxide of the second output driver (68) from voltage changes on the output (16). A level shifter (30) includes multiple cascode devices (46, 48, 50, 52) and switches the first output driver (62) according to the values of a data input (12) and an enable input (14). Switching circuitry (60) coupled to the second output cascode (64) allows the first output cascode (64) to protect the gate oxide of the first output driver (62) and provides extra drive for the output buffer (10).

Abstract: An improved flip-flop is disclosed. The flip-flop (12) includes a latch circuit (22) that receives an input signal and a clock signal. The latch circuit (22) generates an output signal that tracks the input signal during a first portion of the clock signal, and remains constant during a second portion of the clock signal. A master flip-flop (36) receives the clock signal and the output signal of the latch circuit, and generates an output signal that tracks the output signal of the latch circuit (22) during the second portion of the clock signal, and remains constant during the first portion of the clock signal. A slave flip-flop (48) receives the clock signal and the output signal of the master flip-flop and generates an output signal. The output signal tracks the output signal of the master flip-flop (36) during the first portion of the clock signal and remains constant during the second portion of the clock signal. The flip-flop may be incorporated into a shift register (10).

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) A substrate region in the semiconductor substrate is enclosed by a ring of highly doped region (350). An NMOS ESD protection transistor (N1) with its backgate in the enclosed substrate region can be voltage pumped by pump circuitry (N2) in order to trigger bipolar conduction of the ESD protection transistor at a lower voltage. Control circuitry (304) is connected to the signal bond pad and to the gate of amplifier circuitry (P1) to provide a voltage pulse in response to an ESD zap applied to the signal bond pad. PMOS amplifier circuitry (P1) provides an amplified voltage pulse to the pump circuitry with a magnitude approximately equal to the ESD potential on the signal pad so that a strong pump current is provided to the highly doped ring.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: This is a driver circuit 100 for use in an integrated circuit 10 for driving two complimentary signals on output terminals 104 and 106. A single device, such as a Schottky diode 170, prevents voltage breakdown resulting from an externally supplied voltage on either output terminal 104, 106. The single device, such as Schottky diode 170, provides voltage breakdown protection for an output transistor 150 and a complimentary output transistor 152.The single device can be made larger than if two devices were used so that a voltage drop across the device resulting from normal forward current conduction is minimized.

Abstract: Logic circuitry (70, 80, 90) for performing fault detection in a microprocessor (5) is disclosed. The fault detection logic circuitry (70, 80, 90) may be implemented into a scheduler (50) in a floating-point unit (31). Mask register (M) bit positions (M.sub.0 through M.sub.7) store state information relative to registers (52) or other resources in the microprocessor (5) that is to be interrogated upon scheduling of an instruction. The instruction includes an encoded address communicated on register address lines (SA) that is received by the fault detection logic circuitry (70, 80, 90). Pass gates (72) are controlled by the encoded address on the register address lines (SA) to generate a fault indicator (FLT). Partitioning of the decoding of the encoded address may be utilized for optimization of the fault detection operation.

Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. Execution unit S1 has circuitry for clearing or setting a designated bit field in a source operand in one execution phase of an instruction execution pipeline.

Abstract: To provide a type of semiconductor device with high resistance to cracks and having fewer manufacturing steps. Semiconductor device 1 has a substrate having insulating base material 2 mainly made of a thermoplastic polyimide resin. When heated to a temperature above the glass transition temperature, the surface of insulating base material 2 made of thermoplastic polyimide resin melts and exhibits the properties of an adhesive. The adhesive layer is preferred for laminating the metal film for forming conductor pattern 3, and it is preferred for fixing semiconductor IC chip 4 to insulating base material 2 made of thermoplastic polyimide resin. When semiconductor IC chip 4 is fixed on insulating base material 2 made of thermoplastic polyimide resin, the two are brought into contact with each other under a prescribed pressure, and the atmospheric temperature is higher than the glass transition temperature for bonding.

Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. The microprocessor can execute an instruction which shifts a source operand a specified number of bits and saturates the result if a numerical overflow would result from the shift. Execution unit S1 has circuitry for saturating a destination operand by setting all bits within the destination to represent a most positive or a most negative number in a same single instruction execution phase in which the shift would have occurred if not for the overflow. The saturation circuitry examines the source operand prior to shifting to determine if the destination should be saturated.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.