Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: A method for addressing high Work In Process (WIP) conditions for increasing throughput while minimizing risk in a manufacturing line. Selected products to be skipped over during high WIP conditions include determining toolsets having work in process exceeding a certain threshold. For each of the toolsets, products which meet a criteria for skipping are selected. The selected products skip over to the toolset used in a subsequent process step ahead of product failing to meet the criteria for skipping. Solutions to this problem also include the WIP of the current process step, nominal WIP and WIP of subsequent process steps. Candidate lots for skipping process steps are identified by referencing a matrix of parameters that includes yield and criticality.

Abstract: A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.

Abstract: A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region.

Abstract: A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

Abstract: A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL.

Abstract: A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.

Abstract: A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX”) layer including a layer of doped silicate glass. A sacrificial stressed layer is deposited onto the SOI substrate to overlie the SOI layer. Trenches are then etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften and the sacrificial stressed layer to relax, to thereby apply a stress to the SOI layer to form a stressed SOI layer. The trenches in the stressed SOI layer are then filled with a dielectric material to form trench isolation regions contacting peripheral edges of the stressed SOI layer, the trench isolation regions extending downwardly from a major surface of the stressed SOI layer towards the BOX layer.

Abstract: The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.

Abstract: A method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.

Abstract: A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

Abstract: A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the frequency change. The method includes: detecting a change in processing requirements in one of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that a clock frequency change is to occur; achieving a quiescent bus state in each of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that the clock frequency change can occur; and changing the clock frequency of the plurality of integrated circuit chips.

Abstract: A system and a method for effectively determining the measurement sensitivity, repeatability, and probe commonality to assist a test engineer determine if the tester meets the specified resolution at every test. A statistical measurement of inherent tester specifications are provided with the added accumulation of the probe contact resistance during the probing process. It further provides a feedback to the test probe card noise level while testing is in progress. Moreover, the system and the method determine the test probing integrity in-situ when testing integrated circuit chips or wafers, dynamically detecting probing errors, and modifying data associated with defective test probes.

Abstract: A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.

Abstract: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.

Abstract: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

Abstract: A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.

Abstract: An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect.

Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.