Abstract: A symmetrical pressure relief foam mattress includes an upper foam layer placed on a zoned foam layer. A plurality of cylindrical holes are distributed throughout each of a first, a second and a third lateral region of the zoned foam layer. The first lateral region is less than twelve inches wide and has a middle that is within eighteen inches of the top of the zoned foam layer. The third lateral region is also less than twelve inches wide and has a middle that is within eighteen inches of the bottom of the zoned foam layer. The second lateral region has a middle disposed at the center axis of the zoned foam layer. The middle of both the first and third lateral regions is about fifteen inches from the edge of the mattress regardless of which end the consumer chooses to use as the head of the mattress.

Abstract: A memory controller mechanism is operable in a first mode and a second mode. In the first mode, a first memory controller portion of the mechanism can use a first set of data terminals to perform a first external bus access operation (EBAO) and a second memory controller portion of the mechanism can use a second set of data terminals to perform a second EBAO. The first and second EBAO operations may be narrow accesses that occur simultaneously. In the second mode, one of the controllers can use both the first and second sets of data terminals to perform a wider third EBAO. The memory controller mechanism can dynamically switch between first mode and second mode operations. In situations in which one of the sets of data terminals would not otherwise be used, performing wide accesses in the second mode using the one set of data terminals improves bus utilization.

Abstract: A collapsible bed frame that supports a box spring includes side rails and telescoping cross rails. A first hinge connects upper and lower portions of a first side rail that are each at least 35 inches long. A first portion of a cross rail telescopes inside a second portion of the cross rail, and the first portion is connected to the first hinge. Upper and lower portions of a second side rail are connected by a second hinge that includes a slot. The second portion of the cross rail has a tongue that fits into the slot on the second hinge. The side rails also have support legs with flanges that extend above the side rails when the support legs are extended. The first and second hinges also include flanges that together with the support leg flanges prevent the box spring from sliding towards either side of the bed frame.

Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.

Abstract: A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.

Abstract: An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

Abstract: An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.

Abstract: A F/2F waveform generator has a comparator and an analog multiplexer. In a low-cost magnetic card reader application, a magnetic track signal is amplified, filtered, and compared with a threshold signal to create a digital signal output. The analog multiplexer detects changes in state of the digital signal. When a change of state is detected, the analog multiplexer switches among dynamically tunable threshold signals. The selected threshold signal is used for comparison with the magnetic track signal. Switching level detection enables accurate F/2F waveform generation from relatively noisy magnetic track signals, thus improving the robustness of magnetic card readers. The analog implementation eliminates the need for expensive A/D conversion and processing and the design can be readily implemented in a very compact and low-cost package.

Abstract: A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.

Abstract: An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

Abstract: A system involves a plurality of RF-enabled occupancy detectors. Each occupancy detector communicates with and controls an associated plurality of RF-enabled fluorescent lamp starter units. A network master has an RF transceiver used to communicate with the occupancy detectors using a first protocol, thereby retrieving status information from the starter units. The network master also has a second RF transceiver for communicating directly with a cellular telephone using a second protocol. A user can use the cellular telephone to control and interact with the lighting system through the network master, and/or to retrieve status information from the network master. The network master automatically generates and sends email alerts to the user by sending the alerts to an email server. The email server forwards the emails to the cellular telephone via a cellular telephone network. Alerts may, for example, indicate a low battery voltage condition or that a lamp needs replacement.

Abstract: A low-power wireless network involves a master and a plurality of RF-enabled fluorescent lamp starter units. In each of a plurality of intervals, a starter wakes up and listens for a beacon, regardless of whether a beacon is transmitted during that interval or not. The starter operates in a low power sleep mode during the majority of the interval. The master can transmit during the beacon slot time of any interval, but typically only transmits frequently enough to maintain starter synchronization. If the master wishes to communicate with the starters with reduced latency, then the master can transmit a beacon in the next interval. Beacon slot time is varied within the interval (for example, from interval to interval or from group of intervals to group of intervals) in a pseudo-random time-hopping fashion known to both the starters and the master, thereby reducing persistence of collisions with similar networks.

Abstract: A method and system is provided for link layer scheduling for networked applications in a coordinator-based communications system. A network-coordinating device receives a request from a networked application to establish a communications session. The request includes a set of session parameters. The network-coordinating device allocates a first transmission opportunity in response to the request. The network-coordinating device allocates successive transmission opportunities based on the set of session parameters without receiving successive requests. The set of session parameters comprises at least one of a predetermined flow control mechanism, a quality-of-service (QoS) requirement, a bandwidth requirement, and an application type. In one embodiment, the predetermined flow control mechanism is additive increase and multiplicative decrease (AIMD) of transmission control protocol (TCP).

Abstract: A wall plug power monitor accurately measures power consumption of an appliance connected via a wall plug power monitor to AC power supplies of any of the various frequencies used around the world. A three milliohm current sense resistor minimizes power consumption caused by current sensing. Digital oversampling and filtering methods allow for accurate calculation of voltage, current, and power consumption despite line noise and a minimized current sense resistor. Voltage sampling timed to correspond to positive-voltage pulses of voltage measurement signals and current sampling independently timed to correspond to positive-voltage pulses of current measurement signals allow the wall plug power monitor to be used with AC power supplies of varied and varying frequencies. A bit reservation system that scales values to preserve least significant digits allows accuracy while using an inexpensive integer-based processor.

Abstract: A phase locked loop is used to synchronize the switching frequency of a high frequency switching power converter to a clock signal. A switching power converter integrated circuit is a tile-based power management unit and includes an oscillator and multiple tiles of switching power converters. The oscillator generates a clock signal having a clock frequency. A first switching power converter includes a switch and a phase locked loop and switches at a first frequency. The switch has a gate that receives a gate signal. The phase locked loop synchronizes the first frequency to a first integer multiple of the clock frequency. A second switching power converter switches at a second frequency that is a second integer multiple of the clock frequency. The first frequency is synchronized to a multiple of the clock frequency when a second edge of the gate signal coincides with a first edge of the clock signal.

Abstract: An integrated circuit includes a buck converter controller, a PFET, an NFET that is coupled in common drain configuration to the PFET, a first microbump that is connected to the source of the PFET, a second microbump that is connected to the source of the NFET, a third microbump that is connected to the common drain node, a fourth microbump that is connected to a feedback input lead of the controller, and a plurality of other microbumps. The other microbumps are utilized to supply signals to and/or to conduct signals from the controller. A respective one of the four microbumps is disposed to occupy a respective one of the four corners of a square pattern. The other microbumps are disposed in a regular grid along with the four microbumps, but none of the other microbumps is disposed between any two of the four microbumps.

Abstract: A single terminal is used to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is coupled by a low impedance to a voltage source, or 2) is coupled by a medium impedance to the voltage source, or 3) is floating or substantially floating. The circuit asserts a first digital logic signal when the circuit determines that the terminal is coupled by the low impedance to the voltage source. The circuit asserts a second digital logic signal when the circuit determines that the terminal is coupled by the medium impedance to the voltage source. The circuit asserts a third digital logic signal when the circuit determines that the terminal is floating or substantially floating. The terminal and circuit are particular suited for use in a Power Management Unit (PMU) Integrated Circuit.

Abstract: Metallic titanium is continuously produced in an electric-arc furnace under a vacuum by the metallothermic reduction of titanium tetrachloride by a reducing agent such as magnesium. The nanoparticles of titanium obtained from the reduction are simultaneously melted in a bath of molten titanium formed by the heat of an electric arc between a consumable titanium electrode and the molten titanium. A voltage applied across the electrode and the molten titanium is adjusted so that molten titanium is maintained in a cooled crystallizer during the entire process. The molten titanium solidifies on the top of a dummy bar that is drawn down as additional titanium is produced. Upon completion of each iterative reduction reaction, the vaporized reducing agent chloride is pumped out of the electric-arc furnace into a condenser using a vacuum pump. Then, additional reducing agent and titanium tetrachloride are added into the furnace, and the process is repeated.

Abstract: A step-down (buck) switching regulator regulates output current without sensing a current external to a converter integrated circuit. The regulator generates a set current that is indicative of a predetermined current level to which the output current is regulated. The regulator generates a sense current whose magnitude is proportional to an inductor current flowing through a power switch during an on time. During a first time period, the sense current is less than the set current. During a second time period, the sense current is greater than the set current. The output current of the regulator is maintained at the predetermined current level such that the first time period is equal to the second time period when the output current equals the predetermined current level. The set current is compared to the sense current in circuitry inside a bootstrap power generator whose voltage fluctuates with the voltage across the inductor.

Abstract: A method is disclosed for searching for text passages in text documents. The method uses computerized prediction-based and ontology-based semantic language processing. Both the text passages that are to be located, as well as the text of the documents that are searched, are transformed on the basis of surface-syntactic and deep-syntactic information to generate a semantic network structure. The semantic network structure is linguistically processed based on information about other parts of the semantic network structure in order to improve the accuracy of the semantic network structure. Nodes in the semantic network structure are classified by linking the nodes in the semantic network structure to nodes in a pre-existing ontological network structure representing concepts in a language.