Abstract: An asynchronous interface adapter for interfacing two bidirectional data buses. Data transfer between buses may occur simultaneously with provision made for storing bus data from a first bus until a receiver on the second bus is available. The adapter provides bus requests and grant logic, parity checking, time of day clocking, and is adapted to handle variable-length bus messages with the message bytes being carried in a bit-parallel byte-serial form, asynchronously and generally in a bidirectional manner.

Abstract: A membrane type keyboard associated with a data terminal device is disclosed which is sealed to prevent the introduction into the interior elements of the keyboard of water or other types of liquid contaminants encountered during the operation of the terminal device. The keyboard includes an outer frame member which forms an air chamber extending around the perimeter of a raised keyboard, thereby preventing any liquid spilled on the keyboard from reaching the interior elements of the keyboard. The frame member is easily removable from the keyboard, allowing the interior elements to be replaced or exchanged in accordance with the business environment in which the terminal device is to be used.

Abstract: The present invention relates to an integrated circuit package for flat circuit elements such as an integrated circuit chip and an electrical connector for receiving such integrated circuit package. The integrated circuit package comprises a round ceramic carrier or substrate upon which an integrated circuit chip is mounted. The electrical connector of the present invention is a cylindrically shaped hollow socket, the inside diameter of the socket being large enough such that the ceramic substrate may be placed in the hollow. The inside cylindrical wall contains resilient pin-like connections arranged in a circle therein for making contact with a corresponding conductor of the integrated circuit package. The outside surface of the cylindrically shaped electrical connector is threaded for receiving a cap which holds the integrated circuit package against the resilient pin-like connections.

Abstract: A jump return stack is provided in a data processor having a plurality of control registers including a fetch control register and an execution control register. The jump return stack comprises a memory stack, an address register, and a counter-register interposed between the memory stack and the control registers of the data processor. The counter-register is always made to store the latest entry into the memory stack, that is the top of the stack, such that the latest entry into the stack is immediately available to the control registers of the data processor thereby eliminating a memory access to the stack.

Abstract: A method and apparatus for thermally printing on plain paper high resolution fonts such as the ABA's E13B font. In one embodiment, the thermal print head is held stationary while the record medium (like a bank check) and ribbon (containing heat-transferrable ink) are moved, and in a second embodiment, the record medium and the ribbon are held stationary while the printing head is moved. The print head is comprised of printing units with each printing unit having a printing face having resistive heating elements therein. The heating elements are arranged in rows and columns in the associated face to produce a printed dot density of 6.05 N dots per millimeter, wherein N is equal to 1, 2, or 3. Loading of the next pattern of data to be printed is effected while the prior pattern is being "burned" or printed. An R-C circuit is included in the energizing circuit to minimize overheating of the heating elements during repeated energization thereof. Characters or bar codes may be printed by the apparatus.

Abstract: An edge connector wherein an insulated base defines an elongated opening and an insulated carrier is slidably mounted to the base. The carrier is provided with an elongated opening for receiving a printed circuit board. A series of conductors are pivotly coupled between the base and the carrier, such that each of the conductors pivots about one end when the carrier is slid with respect to the base. The length of the conductors is sufficient to come into contact with the edge contacts of the printed circuit board when the printed circuit board is received by the carrier and for transmitting a retaining force to the printed circuit board. A series of resilient pins mounted to the base and in contact with the pivot end of respective conductor of the series of conductors provides along with a spring both the retaining force and the contact force necessary for good electrical contact.

Abstract: An integrated circuit for operatively connecting a plurality of peripheral devices to a processor includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes two independent full duplex, master peripheral ports in which each port provides two character buffering on both input and output channels. Data may be transmitted using two message formats at two different clock frequencies with each channel having simultaneous sending and receiving capabilities. Data processing circuits are located adjacent the first edge which connects to the processor while the port control circuitry is located adjacent the third edge of the chip which connects to the peripheral devices.

Abstract: This invention relates to an error detection circuit for detecting errors in a recovered clock signal from a self-clocking digital data signal. A first flip-flop is alternately set and reset by the recovered clock signal and by a clock source of supposedly equal frequency, respectively. The output of the first flip-flop is sensed by a second flip-flop at the end of a predetermined time period, as determined by the clock source, for determining that a transition in the recovered clock source occurred within the predetermined time period. If no transition occurred within the predetermined time period, the second flip-flop outputs an error signal.

Abstract: Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single conductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffusion mask consisting of a dual layer of silicon dioxide and silicon nitride. Then, source and drains of the p-channel and n-channel transistors are formed. Next, an implantation or diffusion barrier is grown over sources and drains. The oxidation and diffusion mask over all the conductors is then removed and they are all doped simultaneously using a single type impurity.The process may be used to additionally form polysilicon resistors by initially doping the polysilicon to a low level of conductivity. After forming the conductors and resistors they are covered by the oxidation and diffusion mask. Then a resistor mask of either silicon nitride or polysilicon is formed over the resistors to protect them during the high conductivity doping of the conductors.

Abstract: A method and apparatus for removing erroneous data elements from digital images by systemically moving a window memory over the entire area of an image. Each data element in the image is examined with respect to neighboring elements by comparing the contents of the window with a set of masks to determine if a certain data element should be altered.

Abstract: A printing system for printing coded bar elements on a record member include a rotatable drum member having slidably mounted print elements disposed about its periphery. An actuator member positioned adjacent the drum member engages one of the print elements upon movement of the drum member to position a print element adjacent a record member. The actuator member is operated to slide the engaged print element to a printing position enabling the print element to print a coded bar on the record member.

Abstract: A connector assembly for connection to a computer backpanel or the like includes a leadless integrated circuit package and a connector receptacle for receiving the leadless package. The leadless package has two insulating layers and outwardly extending conductors formed on each of the two layers. The insulating layers have contact coupling edges, with the contact coupling edge of one layer extending outwardly of the contact coupling edge of the other layer. Rows of contacts in the receptacle make electrical contact with the conductors on the leadless package at the contact coupling edges. In a second embodiment, the connector assembly includes a leadless integrated circuit package having three insulating layers and outwardly extending conductors formed on each of the three layers.

Abstract: A print head includes a plurality of liquid droplet producing devices in an arrangement wherein the piezoelectric elements are in direct contact with the liquid. The piezo elements are pulsed on demand to cause rapid volume change in the compression chamber to initiate pressure waves therein and to eject ink droplets from the nozzles of the print head.

Abstract: A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus.

Abstract: A method and apparatus for issuing negotiable instruments such as checks from a terminal comprising: first means (identification card reader) for identifying an account number against which a monetary amount of a check to be issued by the terminal is to be charged; second means (handwriting transducer) for inputting into the terminal identification data which will be used in determining whether to accept or reject a user of the terminal as authorized to issue a check against the account number; third means (bank data system) for supplying authorized identification data to the terminal and also for supplying evaluation criteria, such as a current monetary balance, for the account number; entry means (keyboard) for entering check data including the monetary amount; means for comparing (processor) the identification data with the authorized identification data and for generating an accept signal or a reject signal as a result of the comparing; the comparing means also comparing the monetary amount with the evalu

Abstract: A control circuit to disable the operation of a semiconductor microprocessor memory device in event of an unauthorized attempt to access the memory. The memory device is disabled from operation upon removal of the device from the microprocessor. A delayed signal generated outside the memory device enables the control circuit to generate a memory enabling signal. Logic circuit means including a counter generates a signal for a preselected time period during which the delayed signal is required to be generated. Both signals control the enabling of the memory device.

Abstract: A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions. In the course of coplanar processing, the gate electrodes and S/D regions are defined. Selectively prescribed thicknesses of silicon dioxide are then formed over the top and sidewalls of the gate electrodes, as well as the exposed substrate in the S/D regions. Thereafter, a first, silicon nitride layer of controlled thickness is evenly deposited, and is followed by a dry etch step to expose the thin layer of silicon dioxide covering the p-channel FET S/D regions. The temperature stability of silicon nitride protects the n-channel FETs from the effects of the high energy levels and currents associated with the ion implant step used to form the S/D regions of the p-channel FETs. In contrast, the implant ions readily penetrate the thin oxides over the S/D regions of the p-channel FETs. Thereafter, a second, silicon nitride layer of controlled thickness is deposited.

Abstract: A system for measuring program execution time compares all addresses occurring on a memory bus to an upper limit number and a lower limit number to produce a signal which indicates if each address occurring on the memory bus is within a range represented by the upper limit number and the lower limit number. The signal is utilized to either enable incrementing of a counter at a predetermined rate or to increment the counter once for every new address occurring on the memory bus within the range. The contents of the counter represent either the accumulated time of execution of instructions having addresses within the range or the number of instructions executed having addresses within the range. The system includes a display for displaying the contents of the counter.

Abstract: A visual indication of low ink supply wherein a soluble-dye fluid is added to the ink supply and floats on the surface of the ink. The low ink supply is indicated by a change in color printed on the record media by reason of the indicating fluid having different characteristics from the printing ink.