Abstract: Method and apparatus are disclosed for flow control over Point-to-Point Protocol (PPP) data links. A method of negotiating such flow control between two PPP peers is disclosed, along with methods for operating flow control across a PPP link. In one embodiment, flow control frames carry an IEEE802.3x MAC control frame payload—the PPP implementation repackages such frames as MAC control frames and passes them to a MAC, which performs flow control. In another embodiment, flow control frames allow flow control commands to be applied differently to different service classes such that PPP flow can be controlled on a per-class basis.

Abstract: In one embodiment, a removable air filter is mounted proximate to where electrical equipment is mounted in a case. The filter has at least two sections with different finite air impedances. The filter is constructed of a filter media mounted inside of a frame. When the equipment arrangement is modified, the filter can be replaced with another filter with a different impedance profile, such that the air flow remains optimal for many equipment arrangements. The impedance profile can also be tailored to compensate for the characteristic airflow of the case design. Other embodiments are described and claimed.

Abstract: An apparatus to perform hardware-based lossless stateful signature matching is disclosed. In one embodiment, the apparatus comprises a memory and multiple finite state machine (FSM) comparison units operating in parallel to compare packets to signatures to identify matches, if any, between data units in the packets and the plurality of signatures. Each of the FSM comparison units include FSMs having states stored in the memory and at least one transition between pairs of states, and a transition to a new state results in a non-destructive additive operation being performed to store any previous state with the new state.

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low- noise high-power distribution layers in a single mechanically stable board.

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. Specific via designs reduce differential signal distortion due to the via pair, allowing the backplane to operate reliably at differential signal rates in excess of 3 Gigabits per second. In particular, each via passes through nonfunctional conductive pads on selected digital ground plane layers, the pads separated from the remainder of its ground plane layer by a clearance, thereby modifying the impedance of the via and reducing reflections from the stubs created by the via.

Abstract: A high-speed router and method for operation of the core of such a router are disclosed. The disclosure describes switching packet data through a router core serving core ingress and egress ports. The router maintains at least one always-up ingress serial link from each core ingress port to the router core, and at least one always-up egress serial link from the router core to each core egress port. For each core ingress port, packet data is serialized prior to introduction to the router core and then transmitted to the core over that port's ingress serial link. Each core egress port receives a serialized data stream from the router core, which is then deserialized. Within the router core, the serialized data received on each ingress serial link is deserialized into a clocked digital data stream. The digital data streams are switched through a reconfigurable digital switch, reserialized, and transmitted over the egress serial links.

Abstract: A high-speed router and method for operation of the core of such a router are disclosed. The disclosure describes routing packets from core input ports to core output ports by aggregating or queuing packets at router core ingress ports in queues designated for common router core egress ports. A scheduler selects a set of queues, up to one per ingress port, for switching through the router core at each epoch (an epoch is a time slice). When the epoch for a given set of queues arrives, data from each queue is stranded, with one strand sent to each of multiple switch fabric cards. The switch fabric cards operate in parallel to switch the strands from that queue to a common egress port (as configured by the scheduler), where the strands are recombined to reconstruct the original queue data. This architecture can be made fault tolerant, can be made to degrade gracefully when one or more switch fabric cards goes down, and can support increased traffic simply by expanding the number of switch fabric cards.

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract: A data rate controller controls a rate that data is transferred over a backplane in a network processing device. A bandwidth allocator allocates bandwidth to an input port for transmitting data over the backplane to an output port. A bandwidth limiter identifies a maximum allowable bandwidth the input port is allocated on the backplane. A bandwidth tracker identifies an amount of bandwidth currently allocated to the input port for transmitting data over the backplane to the output port. When the current allocated bandwidth is used up, the data rate controller prevents that input port from connecting to output ports through the backplane until more bandwidth is allocated.

Abstract: The invention forms improved ferroelectric (or pyroelectric) material by doping an intrinsic perovskite material having an intrinsic ferroelectric (or pyroelectric) critical grain size with one or more donor dopants, then forming a layer of the donor doped perovskite material having an average grain size less than the intrinsic ferroelectric (or pyroelectric) critical gran size whereby the remanent polarization (or pyroelectric figure of merit) of the layer is substantially greater than the remanent polarization (or pyroelectric figure of merit) of the intrinsic perovskite material with an average grain size similar to the average grain size of the layer. The critical ferroelectric (or pyroelectric) grain size, as used herein, means the largest grain size such that the remanent polarization (or pyroelectric figure of merit) starts to rapidly decrease with decreasing grain sizes.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: This invention provides a semiconductor device with reduced capacitance between adjacent conductors. A porous dielectric layer 28 is formed on conductors 24. A non-porous dielectric layer 30 is formed on porous layer 28, and a second porous dielectric layer 36 is formed on non-porous layer 30. The porous dielectric layers comprise open-pored networks, preferably formed by an atmospheric pressure aerogel process. The present invention allows the construction of semiconductor devices employing multiple layers of conductors with porous low dielectric constant insulation.

Abstract: Single crystal aluminum is deposited on SiGe structures to form metal interconnects. Generally, a method of forming single crystal aluminum on Si.sub.(1-X) Ge.sub.X is presented, including the steps of maintaining the substrate at certain temperature (e.g. between 300.degree. C. and 400.degree. C.) and pressure conditions (e.g. below 2.times.10.sup.-9 millibar) while aluminum atoms are deposited by a vacuum evaporation technique. This is apparently the first method of depositing single crystal aluminum on SiGe surfaces. Novel structures are made possible by the invention, including epitaxial layers 34 formed on single crystal aluminum 32 which has been deposited on SiGe 30. Among the advantages made possible by the methods presented are thermal stability and resistance to electromigration.

Abstract: A stencil mask (10) has a membrane (14) under tensile stress and at least one pattern opening (22) formed through the membrane (14). A plurality of stress relief openings (30) are formed in the membrane for reducing stress-induced distortion of the membrane and the mask pattern. The stress relief openings (30) are positioned to relieve concentrations of stress within the membrane (14) such as those resulting from non-regularities within the pattern. In one embodiment, a screening material (56), less rigid than the membrane (14), is contained within the stress relief openings (30).

Abstract: This invention pertains generally to aging methods suited to aerogel thin film fabrication, and particularly to techniques for improving gel strength and/or aerogel dielectric constant by a rapid aging technique, which avoid damage or premature drying of wet gel thin films during aging. A substrate having a wet gel thin film deposited thereon is contacted with a saturated water vapor atmosphere, preferably at an elevated pressure and a temperature greater than 100.degree. C. The method may comprise a vapor-phase exchange step to remove low boiling point pore liquids such as ethanol prior to or during aging. The method may also comprise a vapor-phase exchange step to replace water in the wet gel with another pore liquid such as acetone to stop the aging process and prepare the wet gel for drying. A vapor-phase aging catalyst (e.g. ammonia) may also be used to enhance the aging process.

Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size. including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: The invention described is an improved dielectric material formed as a film on the surface of a substrate by adding lead to an original perovskite material having an original critical grain size to form a lead enhanced perovskite material, then forming a layer of the lead enhanced perovskite material having an average grain size less than the original critical grain size whereby the dielectric constant of the layer is substantially greater than the dielectric constant of the original perovskite material with an average grain size similar to the average grain size of the layer. The critical grain size, as used herein, means the largest grain size such that the dielectric constant starts to rapidly decrease with decreasing grain sizes. Preferably, the lead enhanced perovskite material is further doped with one or more acceptor dopants whereby the resistivity is substantially increased and/or the loss tangent is substantially decreased. Preferably, the original perovskite material has a chemical composition ABO.