Abstract: An improved slurry composition and method of polishing a workpiece are disclosed. This composition allows use of a neutral pH slurry for chemical-mechanical polishing many surfaces. One disclosed composition comprises 85% water, 4% NaCl, 4% H.sub.2 O.sub.2, and 7% colloidal silica. It has been found that such a slurry produces a high material removal rate for barium strontium titanate (BST) polishing, without damage to the surface of the BST workpiece commonly found with other slurry compositions. This slurry has been found to also polish diamond, silicon carbide, gallium arsenide, and many other difficult-to-polish materials.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti-Al-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Abstract: A modified hydrogen silsesquioxane (HSQ) precursor is disclosed, along with methods for depositing such a precursor on a semiconductor substrate and a semiconductor device having a dielectric thin film deposited from such a precursor. The method comprises coating a semiconductor substrate 10, which typically comprises conductors 12, with a film of a modified HSQ film precursor. The HSQ film precursor comprises a hydrogen silsesquioxane resin and a modifying agent, preferably selected from the group consisting of alkyl alkoxysilanes, fluorinated alkyl alkoxysilanes, and combinations thereof. The method further comprises curing film 14, wherein the inclusion of the modifying agent inhibits oxidation and/or water absorption by the film during and/or after curing. It is believed that the modifying agent modifies film surface 16 to produce this effect.

Abstract: A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 31 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 14 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric.

Abstract: A method of depositing a thin film of a metal oxide by chemical vapor deposition is disclosed. This method is applicable to, e.g., forming thin films of perovskite-phase titanates, zirconates, and/or niobates of divalent metals such as Ba, Sr, and/or Ca. In one example, a first precursor comprises a divalent metal coordinated to carboxylate and polyether ligands, and a second precursor comprises a tetravalent metal coordinated to one or more alkoxide ligands. These precursors are delivered in a mixed stable vapor phase 12 to a preferably heated substrate 14, where a surface-mediated reaction between the two precursors releases a volatile ester and deposits an intermediate compound film 18 comprising the divalent metal, the tetravalent metal and oxygen on the substrate. The substrate may be subsequently annealed to drive off unreacted ligands and/or fully crystallize the intermediate compound film into a perovskite-phase film 20.

Abstract: A modified hydrogen silsesquioxane (HSQ) precursor is disclosed, along with methods for depositing such a precursor on a semiconductor substrate and a semiconductor device having a dielectric thin film deposited from such a precursor. The method comprises coating a semiconductor substrate 10, which typically comprises conductors 12, with a film of a modified HSQ film precursor. The HSQ film precursor comprises a hydrogen silsesquioxane resin and a modifying agent, preferably selected from the group consisting of alkyl alkoxysilanes, fluorinated alkyl alkoxysilanes, and combinations thereof. The method further comprises curing film 14, wherein the inclusion of the modifying agent inhibits oxidation and/or water absorption by the film during and/or after curing. It is believed that the modifying agent modifies film surface 16 to produce this effect.

Abstract: A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size, including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate boron, which has been found to be substantially insoluble in BST, into a BST dielectric film 24. Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Boron included in a BST precursor may be used to form boron oxide in a second phase 30, which is distributed in boundary regions between BST crystals 28 in film 24. It is believed that the inclusion of boron allows for BST grains of a desired size to be formed at lower temperature, and also reduces the leakage current of the capacitive structure.

Abstract: A semiconductor device (10) is illustrated, which is formed on an active region (14) of a semiconductor substrate (12). Device (10) comprises a conductive plug (20) and a barrier layer (22) formed in an opening in an interlevel isolation layer (18). An inner electrode (24) is caused to adhere to the interlevel isolation layer (18) through the use of an adhesion layer (26). High-dielectric-constant layer (28) and an outer electrode (30) are formed outwardly from inner electrode (24).

Abstract: A semiconductor device is disclosed which uses an embedded pillar 38 to prevent damage (e.g. dishing, smearing, overetching) to damascene conductors during fabrication, particularly where such conductors are relatively large. The device comprises an insulating layer 22 formed on a substrate 20 and having a substantially planar upper surface with a plurality of channels 26, 34 formed therein. Channel 34 may be described as comprised of contiguous narrow channel segments (including right segment 40, top segment 41, and left segment 42) enclosing pillar 38, which has a top surface substantially coplanar with the upper surface of layer 22. In one embodiment, pillar 38 is formed integrally as part of layer 22. In alternative embodiments, pillar 38 may be formed from an additional insulating or conducting layer.

Abstract: An improved dielectric material and microcircuit having capacitive elements which employ such a dielectric material are disclosed. The dielectric material comprises polycrystalline barium strontium titanate doped with at least one donor element and having a grain size of less than 1 micron. In the preferred embodiments, the donor element may be Nb, Ta, Bi, Sb, Y, La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er or a combination thereof. The material may be further doped with an acceptor dopant to control resistivity. The microcircuit comprises capacitors having such a dielectric material and connected to a semiconductor substrate which contains embedded circuitry for reading the voltage across a capacitor.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A method and apparatus for removing particulate contaminants from a semiconductor wafer are disclosed. A wafer 10 is held in a wafer holder 12 at cleaning station 14. Cleaning station 14 has a rinse fluid supply system 18 which supplies, e.g. deionized water, to the wafer surface during particle removal. A cleaning pad 20 is mounted on a platen 22, substantially in the plane of wafer 10. Platen 22 is coupled to a drive mechanism 24, which may for example be an electric motor, and drive mechanism 24 is coupled to station 14 by an engagement mechanism 26 which provides vertical displacement to engage pad 20 and wafer 10 for particle removal, and also provides a controlled pad contact pressure during particle removal. In operation, rinse fluid from 18 is supplied to slowly rotating wafer 10, while pad 20 is rotated, preferably at 200 to 600 rpm, and contacted with wafer 10.

Abstract: A stencil mask (10) has a membrane (14) under tensile stress and at least one pattern opening (22) formed through the membrane (14). A plurality of stress relief openings (30) are formed in the membrane for reducing stress-induced distortion of the membrane and the mask pattern. The stress relief openings (30) are positioned to relieve concentrations of stress within the membrane (14) such as those resulting from non-regularities within the pattern. In one embodiment, a screening material (56), less rigid than the membrane (14), is contained within the stress relief openings (30). Methods of forming such masks (10) are also disclosed.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for sample, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: Novel methods of forming capacitors containing high dielectric materials are disclosed. Capacitors are made by forming a layer of conductive metal nitride (e.g. ruthenium nitride, 28), then forming a layer of a high dielectric constant material (e.g. barium strontium titanate, 30) on the metal nitride layer, then forming a layer of a non-metal containing electrically conductive compound (e.g. ruthenium oxide, 32) on the layer of high dielectric constant material. Typically, the high dielectric constant material is a transition metal oxide, a titanate, a titanate doped with one or more rare earth elements, a titanate doped with one or more alkaline earth metals, or combinations thereof. Preferably, the conductive compound is ruthenium nitride, ruthenium dioxide, tin nitride, tin oxide, titanium nitride, titanium monoxide, or combinations thereof. The conductive compound may be doped to increase its electrical conductivity.

Abstract: A semiconductor device and process for making the same with reduced capacitance between adjacent conductors on a connection layer. This technique works best at narrow conductor spacing (less than 1 micron), where the need for lower dielectric constant intralayer insulation materials accelerates. Directional deposition of a dielectric layer 14 at an acute angle relative to the plane of a semiconductor substrate 10 forms bridges between the tops of narrowly spaced conductors 12, resulting in the formation of one or more gas dielectric regions 18. The process is self-aligning, using the shadowing effect of the conductors themselves to mask deposition of dielectric material between them, and only bridges between conductors which are closely spaced. Subsequent deposition of an interlayer dielectric 20 completes a typical structure. The directional deposition method may, for instance, be electron beam evaporation of a material such as SiO.sub.2, Si.sub.3 N.sub.4, polyimide, or amorphous Teflon.

Abstract: The invention described forms improved ferroelectric (or pyroelectric) layer by adding lead to an original perovskite layer having an original ferroelectric (or pyroelectric) critical grain size, then forming a layer of the lead enhanced perovskite layer having an average grain size less than the original ferroelectric (or pyroelectric) critical grain size whereby the remanent polarization (or pyroelectric figure of merit) of the layer is substantially greater than the remanent polarization (or pyroelectric figure of merit) of the original perovskite layer with an average grain size similar to the average grain size of the layer. The critical ferroelectric (or pyroelectric) grain size, as used herein, means the largest grain size such that the remanent polarization (or pyroelectric figure of merit) starts to rapidly decrease with decreasing grain sizes. Preferably, n-type lead enhanced perovskite layer is doped with one or more acceptor dopants whereby the resistivity is substantially increased.