Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti--A--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: Single crystal aluminum is deposited on SiGe structures to form metal interconnects. Generally, a method of forming single crystal aluminum on Si.sub.(1-x) Ge.sub.x is presented, including the steps of maintaining the substrate at certain temperature (e.g. between 300.degree. C. and 400.degree. C.) and pressure conditions (e.g. below 2.times.10.sup.-9 millibar) while aluminum atoms are deposited by a vacuum evaporation technique. This is apparently the first method of depositing single crystal aluminum on SiGe surfaces. Novel structures are made possible by the invention, including epitaxial layers 34 formed on single crystal aluminum 32 which has been deposited on SiGe 30. Among the advantages made possible by the methods presented are thermal stability and resistance to electromigration.

Abstract: A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate organic dielectric materials to form self-aligned contacts (SACTs) reliably, even in deep, narrow gaps. In one embodiment, conductors 26 with insulating conductor caps 28 are formed over a silicon substrate 20 with a thin gate oxide 22. A conformal dielectric layer 30, preferably of thermally-grown oxide, is deposited over this structure, which is then covered with an organic-containing layer 32 and an inorganic cap layer 34 (e.g., CVD TEOS). An etch window 38 is patterned in photoresist layer 36 and used as a mask to etch cap window 39 through layer 34, using layer 32 as an etch stop. A second etch removes organic-containing layer 32 in contact window 41 (and preferably strips photoresist), using conformal layer 30 as an etch stop. A short anisotropic etch may be used to clear conformal layer 30 from gap bottom 43, after which conducting material 40 may be used to make electrical contact to the substrate.