Patents Represented by Attorney, Agent or Law Firm Jeffrey L. Costellia
  • Patent number: 6758986
    Abstract: The production is performed by calcining ferrite magnetic powder in which La is substituted for part of Sr and Ti, Zn, and Co are substituted for part of Fe at temperatures of 1100° C. to 1450° C. The magnetization is improved by substituting Zn for part of Fe, and by substituting Ti for part of Fe for the purpose of charge compensation. In addition, the coercive force is improved by substituting Co for part of Fe, and by substituting La for part of Sr for the purpose of charge compensation. Ti is used for the charge compensation, so that it is possible to reduce the cost.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: July 6, 2004
    Assignee: Sumitomo Special Metals Co., Ltd.
    Inventors: Seiichi Hosokawa, Sachio Toyota
  • Patent number: 6759606
    Abstract: It consists of a body (1) having a sliding key (2) that may activate some side actuators (7, 8), and a central actuator (9), which act over the upper base of the cones (13) of a membrane (14) triggering a determined part of a circuit (15). For this purpose, there are at least two fixed guides (5, 6) between the key (2) and the actuators (7, 8, 9) to guide the sliding of a runner (3) rigidly joined to the key (2) that serves to activate the actuators (7, 8, 9). The runner (3) includes a sliding strip (17) having pivots (18) housed in some crossed slots (19, 20) formed in the fixed guides (5, 6), permitting the guided displacements of the key (2) with the runner (3) in two perpendicular directions to activate the mentioned actuators (7, 8, 9).
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: July 6, 2004
    Assignee: Lear Automotive (EEDS) Spain, S.L.
    Inventor: Josep Maria Fortuny Riera
  • Patent number: 6759681
    Abstract: An object of the present invention is to provide an EL display device having a high operation performance and reliability. The switching TFT 201 formed within a pixel has a multi-gate structure, which is a structure which imposes an importance on reduction of OFF current value. Further, the current control TFT 202 has a channel width wider than that of the switching TFT to make a structure appropriate for flowing electric current. Morever, the LDD region 33 of the current control TFT 202 is formed so as to overlap a portion of the gate electrode 35 to make a structure which imposes importance on prevention of hot carrier injection and reduction of OFF current value.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: July 6, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kunitaka Yamamoto, Toshimitsu Konuma
  • Patent number: 6758629
    Abstract: A postensed celled concrete runway for take off and landing of aircraft is described, also for racetracks, freeways and highways, characterized by a celled structure wherein each cell contains: nervures, a cell base and a cell cover that forms the surface of runway. A core composed of expanded polystyrene is located between the nervures, base and cover, such that the volume weight of the cells is less than subsoil density. The celled structure also contains a leveling means that acts over cells of the celled structure to allow the cells to move in an upward and downward direction so that the runway surface can be leveled when there are sunken areas on the ground.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: July 6, 2004
    Assignee: Postensados y Diseno de Estructuras S.A. de C.V.
    Inventors: Pablo Cortina Ortega, Carlos Gutierrez Sarmiento
  • Patent number: 6759313
    Abstract: In a manufacturing process of a semiconductor device using a substrate having low heat resistance, such as a class substrate, there is provided a method of efficiently carrying out crystallization of a semiconductor film and gettering treatment of a catalytic element used for the crystallization by a heating treatment in a short time without deforming the substrate. A heating treatment method of the present invention is characterized in that a light source is controlled in a pulsed manner to irradiate a semiconductor film, so that a heating treatment of the semiconductor film is efficiently carried out in a short time, and damage of the substrate due to heat is prevented.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: July 6, 2004
    Assignee: Semiconductor Energy Laboratory Co., LTD
    Inventors: Shunpei Yamazaki, Tamae Takano, Koji Dairiki
  • Patent number: 6756010
    Abstract: A method for producing a compact of rare earth alloy powder of the present invention includes: a powder-filling step of filling rare earth allow powder in a cavity formed by inserting a lower punch into a through hall of a die of a powder compacting machine; and a compression step of pressing the rare earth alloy powder while applying a magnetic field, the steps being repeated a plurality of times. When the (n+1)th (n is an integer equal to or more than 1) stage compression step is to be carried out, the top surface of a compact produced in the n-th stage compression step is placed at a position above the bottom surface of a magnetic portion of a die.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: June 29, 2004
    Assignee: Sumitomo Special Metals Co., Ltd.
    Inventors: Tsutomu Harada, Hitoshi Morimoto, Atsuo Tanaka
  • Patent number: 6756640
    Abstract: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: June 29, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Keisuke Hayashi
  • Patent number: 6747627
    Abstract: In a shift register circuit included in a driver circuit for driving an active matrix circuit in an active matrix type display device, a plurality of serial-connected registers constructing register lines are arranged to construct a redundancy shift register circuit. Whether or not each register line has defect is examined by detecting an output of a last register of each register line, then the register line having defect is detected by the examination, a normal register line is selected by a shift register selecting switch, and the serial-connected registers of the selected register line are used in the shift register circuit.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: June 8, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Yuji Kawasaki
  • Patent number: 6743394
    Abstract: A case according to the present invention is used in a sintering process to produce a rare-earth magnet. The case includes: a body with an opening; a door for opening or closing the opening of the body; and supporting rods for horizontally sliding a sintering plate, on which green compacts of rare-earth magnetic alloy powder are placed. The supporting rods are secured inside the body. At least the body and the door are made of molybdenum.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: June 1, 2004
    Assignee: Sumitomo Special Metals Co., Ltd.
    Inventors: Akiyasu Oota, Tsuyoshi Wada, Katsumi Okayama
  • Patent number: 6743700
    Abstract: A semiconductor film having a crystalline structure is formed by using a metal element that assists the crystallization of the semiconductor film, and the metal element remaining in the film is effectively removed to decrease the dispersion among the elements. The semiconductor film or, typically, an amorphous silicon film having an amorphous structure is obtained based on the plasma CVD method as a step of forming a gettering site, by using a monosilane, a rare gas element and hydrogen as starting gases, the film containing the rare gas element at a high concentration or, concretely, at a concentration of 1×1020/cm3 to 1×1021/cm3 and containing fluorine at a concentration of 1×1015/cm3 to 1×1017/cm3.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: June 1, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Noriyoshi Suzuki, Hideto Ohnuma, Masato Yonezawa
  • Patent number: 6743667
    Abstract: An amorphous semiconductor film comprising silicon is provided with a metal element which is capable of promoting a crystallization of silicon. Then, the semiconductor film is crystallized by hating at a relatively low temperature. After introducing impurity ions into source and drain regions of the semiconductor film, the source and drain regions are recrystallized by heating. During the recrystallization, the channel region having crystallinity functions as crystalline nuclei. Accordingly, it is possible to avoid defects occurring in the boundary regions between the channel region and source/drain regions.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: June 1, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masamitsu Hiroki, Yasuhiko Takemura, Mutsuo Yamamoto, Naoaki Yamaguchi, Satoshi Teramoto
  • Patent number: 6739811
    Abstract: There is provided an improved decking assembly including a deck beam and support rail for use in supporting items such as freight in containers, particularly for the purpose of shipping as for example in a highway van trailer. The assembly comprises a pair of elongated tracks, a decking support carriage for each track, and locking means secured to the carriage. The pair of elongated tracks is vertically oriented in opposing relationship to one another. The tracks each have a top surface and a bottom surface, and the top surface has a pair of spaced, inverted, V-shaped grooves with constricted openings, running longitudinally. Each decking support carriage has an outer surface and an inner surface, and spaced, opposing pairs of legs outwardly extending from the inner surface. The pairs of legs form complementary, inverted V-shapes to matingly engage within the grooves on the tracks for secure, guided, sliding movement within the tracks.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: May 25, 2004
    Assignee: Aero-Kit Industries Inc.
    Inventor: Brian W. Petelka
  • Patent number: 6737717
    Abstract: There is provided a semiconductor device including a semiconductor circuit formed by semiconductor elements having an LDD structure which has high reproducibility, improves the stability of TFTs and provides high productivity and a method for manufacturing the same. In order to achieve the object, the design of a second mask is appropriately determined in accordance with requirements associated with the circuit configuration to make it possible to form a desired LDD region on both sides or one side of the channel formation region of a TFT.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: May 18, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Hideaki Kuwabara
  • Patent number: 6724037
    Abstract: A nonvolatile memory transistor with multi values being capable of suppressing a short channel effect is provided. In an active region of a memory transistor, stripe-shaped impurity regions (pinning regions) are formed in a channel length direction. The pinning regions suppress the spread of a depletion layer of a drain region, and a short channel effect caused by fine processing. Furthermore, in a memory transistor using pinning regions, by assigning one value or one bit of data to each channel forming region, the memory transistor is allowed to have multi values. More specifically, the present invention has a configuration in which a floating gate electrode is provided on each of a plurality of channel forming regions via a first gate insulating film, and an electric potential can be applied independently to a plurality of pinning regions.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: April 20, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 6723590
    Abstract: A linear laser light which has an energy and is to be scanned is irradiated to a semiconductor device formed on a substrate, and then the substrate is rotated to irradiate to the semiconductor device a linear laser light which has a higher energy than that of the irradiated linear laser light and is to be scanned. Also, in a semiconductor device having an analog circuit region and a remaining circuit region wherein the analog circuit region is smaller than the remaining circuit region, a linear laser light having an irradiation area is irradiated to the analog circuit region without moving the irradiation area so as not to overlap the laser lights by scanning. On the other hand, the linear laser light to be scanned is irradiated to the remaining circuit region.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: April 20, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Naoaki Yamaguchi, Yasuhiko Takemura
  • Patent number: 6719370
    Abstract: A tip-up seat assembly with a backrest, adapted to be secured to a supporting structure in a generally upright orientation, a corresponding seat member adjacent the backrest, hingedly mounted for rotation between an open position wherein the seat member is substantially horizontal and a folded position wherein the seat member is tilted upwardly toward the backrest, biasing device for biasing the seat member toward the folded position, and a tilt-limiter configured to resiliently restrain the seat member in an intermediate position thereby avoiding inadvertent rotation of the seat member into the folded position.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: April 13, 2004
    Assignee: Viscount Plastics (NSW) Ltd.
    Inventors: Kevin Michael Hannon, Philip Duncan Loader
  • Patent number: 6713323
    Abstract: A semiconductor device is manufactured by a method in which the number of heat treatments at a high temperature (600° C. or higher) is reduced to thereby achieve a process at a low temperature (600° C. or lower), and a simplified process and improvement in throughput are realized. An impurity region to which a rare gas element (also called a rare gas) is added is formed on a semiconductor film of a crystalline structure by using a mask. Gettering is performed in such a manner that a metallic element contained in the semiconductor film is caused to segregate in the impurity region by heat treatment. The impurity region is thereafter used as a source or drain region.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: March 30, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Takashi Hamada, Satoshi Murakami
  • Patent number: 6713783
    Abstract: A liquid-crystal electro-optical device capable of compensating for the operation of any malfunctioning one of TFTs (thin-film transistors) existing within the device if such a malfunction occurs. Plural complementary TFT configurations are provided per pixel electrode. Each complementary TFT configuration consists of at least one p-channel TFT and at least one n-channel TFT. The input and output terminals of the plural complementary TFT configurations are connected in series. One of the input and output terminals is connected to the pixel electrode, while the other is connected to a first signal line. All the gate electrodes of the p-channel and n-channel TFTs included in said plural complementary TFT configurations are connected to a second signal line.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: March 30, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akira Mase, Masaaki Hiroki
  • Patent number: 6709906
    Abstract: In producing a semiconductor device such as a thin film transistor (TFT), a silicon semiconductor film is formed on a substrate having an insulating surface, such as a glass substrate, and then a silicon nitride film is formed on the silicon semiconductor film. After that, a hydrogen ion, fluorine ion, or chlorine ion is introduced into the silicon semiconductor film through the silicon nitride film, and then the silicon semiconductor film into which an ion is introduced is heated in an atmosphere containing hydrogen, fluorine, chlorine or these mixture, to neutralize dangling bonds in the silicon semiconductor film and reduce levels in the silicon semiconductor film.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: March 23, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoaki Yamaguchi, Hongyong Zhang, Satoshi Teramoto, Hideto Ohnuma
  • Patent number: 6709901
    Abstract: A pixel TFT formed in a pixel region is formed on a first substrate by a channel etch type reverse stagger type TFT, and patterning of a source region and a drain region, and patterning of a pixel electrode are performed by the same photomask. A driver circuit formed by using TFTs having a crystalline semiconductor layer, and an input-output terminal dependent on the driver circuit, are taken as one unit. A plurality of units are formed on a third substrate, and afterward the third substrate is partitioned into individual units, and the obtained stick drivers are mounted on the first substrate.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: March 23, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Yasuyuki Arai, Hideaki Kuwabara