Patents Represented by Attorney Jenkins, Wilson & Taylor, P.A.
  • Patent number: 6968316
    Abstract: Systems, methods, and computer program products for generating a narrative financial analysis of a financial statement of a business entity are provided. Financial information about a business entity is obtained from a user. A set of financial values is calculated based on the received financial information. The calculated values are compared to values calculated for the same business entity over time or to different business entities in the same industry. Scores are assigned to the financial values based on the comparison. For each combination of scores, text is dynamically selected to generate a narrative financial analysis report. The narrative financial analysis report includes text that explains the meaning of each combination of scores in a narrative format.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: November 22, 2005
    Assignee: Sageworks, Inc.
    Inventor: Brian Hamilton
  • Patent number: 6968048
    Abstract: A method and system for generating and providing existing and new message accounting records in a standard format using call data obtained from switching and/or signaling networks is disclosed. A system for providing augmented billing messages includes a message accounting record creation apparatus being in communication with a signaling network and a switching network. The message accounting record creation apparatus receives call records from the signaling network and message accounting records from the switching network and outputs augmented message accounting records. Each of the augmented message accounting records is generated using one of the signaling network call records and one of the switching network message accounting records.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: November 22, 2005
    Assignee: Tekelec
    Inventors: Kenneth Andrew Moisey, John Unsworth, David S. Carson
  • Patent number: 6967133
    Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 22, 2005
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Amon, Jürgen Faul, Ulrike Gruening, Frank Jakubowski, Thomas Schuster, Rudolf Strasser
  • Patent number: 6966169
    Abstract: Mowing machine chute cleaner apparatuses and methods are disclosed including a housing and at least one rotatable blade positioned at least partially within the housing for cutting grass. The mowing machine includes a discharge chute for discharge of cut grass, wherein the discharge chute defining an exit opening, and the mowing machine includes a cover flap attached to the grass mowing machine and being movable from a closed position covering the discharge chute exit opening to an open position wherein the discharge chute exit opening is uncovered by the cover flap. The mowing machine also includes a movable clearing flap attached to the grass mowing machine which can be moved in a clearing motion through at least a portion of the discharge chute by movement of the cover flap to at least partially clear cut grass from the discharge chute.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 22, 2005
    Assignee: Honda Motor Co., Ltd.
    Inventor: Christopher M. Osborne
  • Patent number: 6965660
    Abstract: A digital phase-locked loop is provided having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock signal in a normal operating state of the digital phase-locked loop. The phase-locked loop can include a phase detector for identifying a phase deviation between the reference clock signal and a feedback clock signal. Further, the phase-locked loop can include a resettable counter, which generates a digital phase deviation signal corresponding to the identified phase deviation. The phase-locked loop can also include a resettable digital filter for filtering the digital phase deviation signal. Further, the phase-locked loop can include an oscillator circuit for generating the output clock signal as a function of a filtered digital phase deviation signal. The phase-locked loop can also include a resettable feedback frequency divider which divides the output clock signal for generating the feedback clock signal.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: November 15, 2005
    Assignee: Infineon Technologies AG
    Inventor: Klaus Strohmayer
  • Patent number: 6965592
    Abstract: A distributed gateway includes distributed gateway routing elements co-located with SS7 network elements. Each distributed gateway routing element performs an SS7 routing function, such an MTP level 3 routing function. The distributed gateway routing elements communicate with each other over a virtual bus that guarantees quality of service for SS7 message packets. Accordingly, the distributed gateway routing elements set quality of service parameters in the SS7 message packets that are forwarded over the virtual bus.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: November 15, 2005
    Assignee: Tekelec
    Inventors: Robert John Tinsley, Peter Joseph Marsico, Lee Barfield Smith, Virgil Elmer Long, Gregory Allen Hunt
  • Patent number: 6960984
    Abstract: Methods and systems for compensating magnetic current loops provide current magnitude and phase uniformity within the magnetic current loops. A magnetic current loop is divided into k sections. Each of the k sections has a series reactance. Series reactive compensation is added to each of the k sections such that the reactive compensation substantially cancels the series reactance of each section. Adding reactive compensation to the loop that cancels the series reactance of each section of the loop provides current magnitude and phase uniformity along the loop at any given instant in time. As a result, the magnitude and phase of the magnetic field at a point in space can be controlled with precision to achieve a desired result, such as precise field cancellation or precise field generation.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: November 1, 2005
    Assignees: University of North Carolina, dBTag, Inc.
    Inventors: Leandra Vicci, Wayne D. Dettloff
  • Patent number: 6961882
    Abstract: The present invention provides a memory chip (100) which can be operated in a normal mode and in a test mode (TM) and which has a device (102) for outputting data from the memory chip (100) and a device (104) for enabling the device (102) for outputting data when the test mode (TM) has been activated. The device (104) for enabling the device (102) for outputting data has a device for masking data so that only particular portions of the data are output when a data masking state (DQM) has been activated.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: November 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Dobler Manfred, Finteis Thomas
  • Patent number: 6960524
    Abstract: The invention relates to a method for production of a metallic or metal-containing layer (5) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon- or germanium-containing layer before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements or the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: November 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Thomas Hecht, Bernhard Sell, Annette Saenger
  • Patent number: 6958256
    Abstract: The present invention relates to a process for the back-surface grinding of wafers using films which have a support layer, which is known per se, and an adhesion layer which can be polymerized in steps, and to films which include such an adhesion layer which can be polymerized in steps, and to the use thereof.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Infineon Technologies AG
    Inventors: Michael Rogalli, Manfred Schneegans
  • Patent number: 6959076
    Abstract: Method and systems for providing triggerless screening services include a triggerless screening service routing node and a message processing platform. The triggerless screening service routing node identifies call setup messages that require one or more call screening services and diverts the messages to a message processing platform. The message processing platform performs at least one screening action on the call setup messages and modifies the messages to include the type and result of the screening action.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: October 25, 2005
    Assignee: Tekélec
    Inventors: James Tjin-Tek Chang, Thomas Matthew McCann, Peter Joseph Marsico, Allen Woodward Haley, Jr., Linda Ann Rushnack
  • Patent number: 6956820
    Abstract: Methods and systems for providing voice over IP traffic engineering and path resilience using a network-aware media gateway are provided. In a media gateway, voice over IP hosts are assigned a first set of IP addresses. Network interfaces in the media gateway are assigned a second set of IP addresses that differ from the first set of IP addresses. Per-interface routers advertise reachability information from at least one of the voice over IP hosts via multiple interfaces and participate in network routing protocols to generate per interface routing tables. Voice over IP path lists may be generated based on the per interface routing tables. Internal costs may be assigned to the associations between the voice over IP hosts and the interfaces based on traffic engineering criteria.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: October 18, 2005
    Assignee: Santera Systems, Inc.
    Inventors: Rupert Zhu, David Z. Lu, San-Qi Li, Edward Y. Qian
  • Patent number: 6955677
    Abstract: A fastening apparatus includes a fastener and a fastener receiving member. The apparatus enables the fastener to be affixed to the fastener receiving member at a variable insertion angle selected by the user. The fastener includes an elongate section and an adjoining head section. Both the elongate section and the head section are threaded. The fastener receiving member includes one or more apertures through which one or more corresponding fasteners can be inserted. Each aperture includes a contact region formed or disposed on an inside surface defining the aperture. The contact region includes a porous matrix of protrusions or fiber metal having a density and strength sufficient to render contact region tappable by the thread of the head section of the fastener. The thread on the head section is driven into the contact region at the selected insertion angle.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: October 18, 2005
    Assignee: The University of North Carolina at Chapel Hill
    Inventor: Laurence E. Dahners
  • Patent number: 6957373
    Abstract: An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: October 18, 2005
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Ernst, Justus Kuhn, Jens Luepke, Peter Poechmüller, Gunnar Krause, Jochen Mueller, Michael Schittenhelm
  • Patent number: 6954526
    Abstract: A network element for routing a calling name (CNAM) query message through a communications network includes a communication module capable of receiving a CNAM query message from and transmitting the CNAM query message to a communications network. A CNAM query routing information database stores CNAM query routing information for at least one CNAM database. A CNAM query routing address translation process performs a lookup in the CNAM query routing information database based on information contained in the query message and determines whether to route the query message to a national CNAM database based on results from the database lookup.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: October 11, 2005
    Assignee: Tekelec
    Inventors: Dean Douglas Glenn, Peter Joseph Marsico
  • Patent number: 6954794
    Abstract: Methods and systems for exchanging reachability information and for switching between redundant interfaces in a network cluster are disclosed. Nodes in the network cluster are connected via redundant links and exchange reachability messages at periodic intervals. Each node includes a kernel routing table used to route messages and a reachability application routing table for storing reachability information used to update entries in the kernel routing table. Each node executes a predetermined algorithm for selecting entries in the reachability application routing table to be written to the kernel routing table.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: October 11, 2005
    Assignee: Tekelec
    Inventors: Joseph Michael Rudd, Benjamin Crawford Robinson, Jeffrey Lynn Ellis, David F. Knierim
  • Patent number: 6953315
    Abstract: An apparatus and method for controlling the flow of a process material from a higher pressure environment to a lower pressure environment is provided. Each of a first and second chamber is divided into a product region and a control region by a flexible boundary. Inlet and outlet flow control devices provide fluid communication between each product region and a material input line and a material output line, respectively. A chamber control device is arranged to provide fluid communication between the control region of each chamber, which is filled with a non-compressible fluid. As product fills the product region of one chamber, fluid is displaced from the corresponding control region and into the control region of the other chamber. As the control region of the other chamber expands, product is forced out of the corresponding product region and into the material output line. The product region of each chamber is alternately filled and emptied to produce a continuous transport of material.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: October 11, 2005
    Assignee: North Carolina State University
    Inventor: Gary Dean Cartwright
  • Patent number: 6951935
    Abstract: Novel methods of synthesizing heteroatom-containing porphyrins and metalloporphyrins are disclosed. Novel heteroatom-containing porphyrin and metalloporphyrin compounds are also disclosed. The new methods advantageously utilize metal-catalyzed cross-coupling and amination reactions to produce porphyrin compounds useful in a variety of practical applications.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: October 4, 2005
    Assignee: University of Tennessee Research Foundation
    Inventors: X. Peter Zhang, Ying Chen, Guangyao Gao, Andrew J. Colvin
  • Patent number: 6951758
    Abstract: A method for the production of adeno-associated virus stocks and recombinant adeno-associated virus stocks that are substantially free of contaminating helper virus is described. The method utilizes transfection with helper virus vectors to replace the infection with helper virus used in the conventional method.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: October 4, 2005
    Assignee: The University of North Carolina at Chapel Hill
    Inventors: Forrest K. Ferrari, Xiao Xiao, Richard Jude Samulski
  • Patent number: 6947548
    Abstract: Driver circuit for at least one subscriber terminal, comprising a first driver (14) for amplifying the power of a direct-voltage signal applied for supplying power to the subscriber terminal, the first driver (14) being supplied by a first supply voltage (V1), and comprising a second driver (37; 37a, 37b), following the first driver, for modulating high-frequency signal currents onto the power-amplified direct-voltage signal.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: September 20, 2005
    Assignee: Infineon Technologies AG
    Inventor: Thomas Ferianz