Abstract: A method of partitioning design shapes, in an E-beam lithography system, into subshapes such that a constant dose may be applied to an E-beam sensitive resist within each subshape. Within each subshape the constant dose corresponds to an approximation to an indicator function, indicative of the degree of the proximity effect, such as the effective exposure of the resist from backscattered electrons or the required dose. The error of the approximation is equal to a predetermined value for each subshape, and can depend upon the position of the subshape within the shape and the influence of errors in the applied dose at that position on the position, on development, of the edge of the shape.

Abstract: A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in a row direction while the word lines run in a column direction. Transfer transistors are designed to be shared with the same drain junction and the same bit line contact in order to save area. A choice of at least two described embodiments are provided. In one embodiment, referred to as the offset bit line structure, the bit lines are constructed by using two layers of interconnection lines to connect the interdigitated cells associated to it. By connecting the bit line contacts and with two different interconnecting layers and in an alternating row order, the true and complement bit lines and will run parallel to both sides of the memory array.

Abstract: An object of the present invention is to provide an optical system for lithography wherein the zero order component of the main lithographic image is unobstructed and the zero order component in the ghost image is removed. The optical system includes a beamsplitter component and a condensor lens structure for illuminating a lithographic mask from a range of directions which excludes a range of directions that are sufficiently close to the axis to add undesired background to the exposure field after multiple reflections with the lens. The optical system further includes an excimer laser and a lens system having an array of stops for intercepting multiple images of the excimer laser after they reflect from the primary wafer image or other surfaces such as the mask or lens surfaces.The illuminating zero-order beams reflect obliquely off the wafer after contributing to the image, where they are then refocussed to the opposite side of the pupil (the primary mirror).

Abstract: A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than the first voltage. The reduced bit-line swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

Abstract: A method of proximity correction in an E-beam lithography system wherein each design shape is contracted by a predetermined bias and the E-beam dose required at any given point of the design is determined such that each of the design shapes is enlarged, on development, by the value of the predetermined bias, the determination of the E-beam dose being made in accordance with a predetermined relationship between an indicator, such as the electron backscatter, and the required E-beam dose, the indicator being defined for a plurality of points arranged on a coarse grid on the design and being indicative of the degree of the proximity effect at the respective point, the determination of the required dose being made by solving, at each of the plurality of points on the design, an integral equation relating the indicator to the E-beam dose distribution.

Abstract: An electrically programmable and electrically erasable memory cell (EEPROM) formed in a silicon body is described. The cell includes a silicon body or substrate with shallow trench isolation regions disposed therein. First and second spaced-apart source and drain regions of a first conductivity type are provided with a channel region in between. A first gate member, a floating gate, which is completely surrounded by insulation extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. A second gate member, a control gate, includes a portion which extends over the floating gate. The control gate extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. The channel region beneath the floating gate has both a highly doped portion and a lightly doped portion.

Abstract: A lens system having discrete variations of focal length at discrete distances of radius outward from the optic axis for focussing light of plural wavelengths. The lens system which directs a laser beam onto a target for ablation or exposure applications includes one set of lens elements to handle short wavelength light used for ablation or exposure applications, and another set of lens elements to handle long wavelength light used for alignment applications. The lens system which provides for the ablation or exposure functions at short wavelength and for through-the-lens alignment at a longer wavelength and higher numerical aperture consists of three elements. Two outer lens elements are made entirely of fused quartz. An inner element disposed between the two outer lens is composed of any material such as optical glass. The inner lens element has a hole ground through its center.

Abstract: A method for fabricating bipolar and CMOS devices in integrated circuits using W as a local interconnect and via landing pad for bipolar and CMOS devices. The method includes the forming of an oxide/silicon bilayer above a local interconnect of tungsten/titanium wherein the oxide is patterned as a mask for the silicon/tungsten/titanium reactive ion etch, and the silicon layer above the tungsten/titanium layer is used as an etch stop for a via etch. The silicon layer is then reacted and converted to titanium silicide after the via etch to provide a low resistance path in the via from the local interconnect in a self aligned manner.

Abstract: A method is disclosed for fabricating a DRAM trench capacitor with multiple-pillars inside the trench for increased surface area.A thin pad oxide of a few tens of nonometers is grown on a silicon substrate. A layer of silicon nitride is deposited and another layer of oxide is then deposited. This provides the ONO stack. Then a layer of polysilicon, a layer of nitride, and a layer of large-grained polysilicon are deposited sequentially. Then, a trench is defined by a lithographic mask and the exposed large-grained polysilicon is etched in CF.sub.4. Since CF.sub.4 etches the polysilicon and nitride 20 at almost the same rates, the topographical features existed in the polysilicon layer is copied to the nitride layer. The nitride layer is partially etched. The RIE etching gas is then changed to a mixture of HBR, SiF.sub.4, Helium, and NF.sub.3 which gives a very directional polysilicon etching with a good selectivity to nitride and a very high selectivity to oxide.

Abstract: Lightly Depleted PMOS (LDP) substrate-plate trench-capacitor (SPT) cell Array architecture is disclosed including three types of devices: An enhancement NMOS transistor (ENMOS) which has a n+ poly gate with a positive threshold voltage range, an enhancement PMOS transistor (EPMOS) having a p+ poly gate with a negative threshold voltage range, and a lightly depleted PMOS transistor (LDPMOS) having a p+ poly gate. The LDPMOS is used as the access transistor in the SPT cell with body biased at the power supply voltage VDD, and can also be used in the write drivers. A sense amplifier is included which is a CMOS cross-coupled latch. An n-well is biased at a lower voltage than VDD, such as (VDD--Vg) where Vg is the silicon bandgap, and the lower thresholds enhance faster sensing. The CMOS cross-coupled latch is activated by turning on latching devices.

Abstract: An apparatus for modifying, such as etching or developing, selected areas of a wafer is disclosed including a rotatable turntable upon which a wafer having a surface to be etched is mounted. A delivery nozzle for directing modifying fluid onto the wafer surface is disposed over the wafer surface at a first location. At least one structure for removing the modifying fluid, such as a vacuum nozzle is positioned over the surface of the wafer at a second location. The modifying fluid moves across the wafer surface by centrifugal force away from the first location and is removed at the second location. The surface area of the wafer between the first and second locations is modified by the etching fluid.

Abstract: A technique for making a high resolution X-ray mask with high aspect ratio absorber patterns sufficient for use in X-ray lithography wherein a thin resist layer is used to provide a low contrast mask, and then an X-ray exposure is used to increase the aspect ratio of the absorber to increase the contrast of the mask. The mask is first patterned with an e-beam resist exposure and development step, and the plating of the base material is activated by a reactive ion etch followed by electroplating. The resist is removed and the mask is coated with a negative acting X-ray resist. The back of the mask is exposed to X-rays wherein the existing absorber acts as an X-ray mask to expose the desired areas of the resist. The resist is removed after development, reactive ion etching and electroplating resulting in a mask with high contrast.

Abstract: A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in a row direction while the word lines run in a column direction. Transfer transistors are designed to be shared with the same drain junction and the same bit line contact in order to save area. A choice of at least two described embodiments are provided. In one embodiment, referred to as the offset bit line structure, the bit lines are constructed by using two layers of interconnection lines to connect the interdigitated cells associated to it. By connecting the bit line contacts and with two different interconnecting layers and in an alternating row order, the true and complement bit lines and will run parallel to both sides of the memory array.

Abstract: A transmission grid is disposed in a conventional focussed ion beam system which includes an ion beam source emitter or ion gun, electrodes to turn the ion beam off and on, a beam defining aperture and electrostatic lenses to focus the ion beam onto a target. The elements of the ion beam system are disposed in a chamber which is provided with an inlet port and an outlet port. Gas is introduced into chamber via the inlet port where it is ionized by the ion beam into an ion plasma to be used to deposit materials onto the target. The transmission grid, is interposed which is a fine mesh, passive element is located in the path of the ion beam and reduces the ion beam current density by a desired value. The transmission grid may be configured with a variety of different transmissions so the current density can be adjusted in different increments depending on the gas/type of deposition to be performed.

Abstract: An X-ray mask structure for X-ray lithography which can be adjusted by applied force to provide variable magnification of a pattern on the mask membrane. The applied force is provided by the heat expansion of a deformable member and the resultant stress on a support ring. A circular patterned mask membrane is supported in a ring composed, for example, of silicon or silicon-pyrex. The support ring contains a concentric aluminum ring having an embedded circular heating element. The heating element causes expansion of the aluminum ring which causes mechanical stress in the support and expansion of the mask membrane. Expansion of the mask membrane results in a corresponding magnification of the pattern thereon.

Abstract: An ion beam structure includes a gas container, such as a cylindrical can having first and second apertures through the center of the top and bottom walls respectively of the container such that a narrow ion beam is passed through the apertures and the center axis of the can and onto a target specimen such as a mask or chip or other article of manufacture disposed closely below the bottom of the can. The can may further include deflection means for applying voltages and/or magnetic fields to locations on the can (i.e., top, bottom, sides) to direct secondary charged particles such as electrons emitted from the specimen onto an electron detection means such that the structure functions as an imaging system. The electric and/or magnetic fields may be employed to increase the collection efficiency of the detector and thereby improve the quality of the image by increasing the signal to noise ratio.

Abstract: An X-ray mask membrane 12 is discussed wherein a cantilever and tip portion such as used on an atomic force or scanning tunneling microscope are fabricated directly as part of the mask. The mask is located over a wafer and the vertical (z) motion of the tip with respect to the wafer is achieved with a piezoelectric device which is mounted on a movable support above the cantilever. Piezoelectric device may be a tube having an electrode divided into quadrants so that the end of the tube could be positioned in three dimensions to allow for alignment of the end of the tube to the cantilever tip. X and Y motion of the tip and the mask membrane relative to the wafer is achieved by mounting the wafer on an x-y stage driven by piezoelectric or other transducers. The wafer includes a raised alignment mask on its upper surface. The wafer, mask membrane, and z piezoelectric tube are held rigidly but adjustably with respect to each other by a mechanical fixture.

Abstract: A simple effective and fairly stable boron source that is easy to prepare and simple to operate under UHV processing conditions is disclosed. The method for fabricating this boron source includes the in situ alloying of boron into a high melting point elemental semiconductor material, preferably silicon, in the hearth of an electron beam evaporator. A supersaturated solution of boron in silicon is created by melting the silicon and dissolving the boron into it and quenching the solution. The boron needs to be of high purity and may be in the form of crystalline granules for this to take place under controlled conditions and moderate power levels. When silicon is evaporated from this resultant silicon-boron alloy source, the silicon evaporates uncontaminated from a molten pool of the alloy in the center of the hearth. A segregation of boron into the liquid phase occurs and a segregation takes place from this molten phase into the vapor phase that is being evaporated from the pool.

Abstract: A P- semiconductor material substrate which has been ion-implanted with N-type dopants to form an N+ subcollector layer is annealed in Argon to further remove implant damage and drive the dopant ions deeper into the P substrate. Next a lightly doped N- epitaxial layer is grown on the N+ subcollector layer. This forms the blanket collector. A P- well region is formed by growing a pad oxide of 10 nm on the N-epi layer and a 200 nm layer of nitride is then deposited on top of the layer oxide. A photoresist etch mask is used to pattern the P- well region. A reactive ion etch is performed through the dielectric oxide and nitride layers, through the epitaxial layer and stopping in the subcollector layer. A layer of low temperature expitaxial material is grown over the structure using ultra-high vacuum/chemical vapor depositions such that the epitaxial layer extends above the surface of the epitaxial layer and includes a P+ heavily doped layer and a lightly P-doped surface layer.

Abstract: A crystal oscillator circuit wherein first and second transistors are connected to form a differential pair. The second transistor functions as an inverting gain stage for the oscillator and two capacitors are provided to complete a feedback path in series with a crystal which essentially functions as an inductor. The capacitors are large enough to minimize the effect of device parasitics and small enough for monolithic implementation. The square-wave output from the circuit is completely isolated from the oscillator gain stage, thus subsequent logic gates will not have any effect on the oscillator performance and DC-coupling can be used without a need for AC-coupling capacitors. The circuit is completely monolithic, requiring only an external crystal. The circuit inherently suppresses the fundamental frequency without a need for a tank circuit or a feedback resistor and does not influence the biasing.