Abstract: A buried contact structure to decrease the spreading resistance of various circuit elements of semiconductor devices such as transistors and for reducing the resistance of polysilicon wires typically used in short lengths to connect the circuit elements to other metallic wires. The buried contact structure more specifically includes a phosphorous diffusion superimposed on the field implant which includes the source and/or drain of the transistor device. An overlayed layer of polysilicon is then disposed to make contact with the buried contact diffusion. The field implant used for the source and drain may, for example, be boron. The buried contact structure has a lower resistance than the field implant and therefore provides a lower resistance path for the device current.

Abstract: An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor.

Abstract: This atomic force microscope includes a pointed tip (1) mounted on top of an oscillating crystal (2) which is translatable in xyz-directions by a conventional xyz-drive (4). A potential applied to a pair of electrodes (5, 6) coated on opposite faces of the crystal (2) causes the latter to oscillate with its resonance frequency. As the tip (1) is approached to a surface to be investigated, the frequency of oscillation of the crystal deviates from its original frequency. This deviation can be used in a feedback loop to control the distance in z-direction of the tip (1) from the surface being investigated and to plot an image of the contour of each scan performed by the tip (1) across the surface.

Abstract: A testing or sampling probe to determine the response of electrical circuits or devices to ultrafast electrical pulses. The probe is detachable from the device being tested. The probe includes a transparent substrate though which optical pulses are focused or directed onto a photoconducting gap. The probe further includes a transmission line associated with the photoconductive gap, and which terminates at a tapered end of the probe in contacts which are placed on the device under test.

Abstract: A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding and precharging. The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.

Abstract: A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .phi.PC line is included for receiving a .phi.PC precharge clock signal thereon and a .phi.R line is provided for receiving a .phi.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state.

Abstract: A circuit means for interfacing between small emitter-coupled-logic (ECL) circuit voltage levels and larger field effect transistor (FET) circuits voltage level. The circuit interface means includes a source-follower stage wherein a first transistor device is ratioed relative to a second transistor device, so that a high percentage of an input voltage level signal to the first transistor device appears at a node between the first and second transistor devices, having been level shifted downward by greater than or equal to an n-channel threshold voltage. The percentage is enhanced by applying the complement of the input voltage level signal to the gate of the second transistor device. A gain stage is connected to the source-follower stage and includes third and fourth transistor devices wherein gain is developed by applying the level shifted input signal to the source of the fourth transistor device and the complement of the input signal directly to the gate of the fourth transistor device.

Abstract: A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor 14 has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls of the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts.

Abstract: A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate and an epitaxial layer disposed thereon. A relatively deep polysilicon filled trench is disposed in the epitaxial layer and substrate structure, the deep trench having a composite oxide/nitride insulation layer over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer over the deep trench region, the shallow trench having an oxide insulation layer on its vertical and horizontal surfaces thereof. A neck structure of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench to the bottom surface of the shallow trench.

Abstract: A novel sense amplifier and decoupling device structure for integrated circuit memories wherein an embodiment of a cross-coupled sense amplifier includes two PMOS devices, the gates of which devices are grounded and clamp the downward voltage swing of the memory bitlines to the absolute value of the threshold voltage (VTP) of the grounded-gate PMOS devices in the sense amplifier. This limited voltage swing does not affect charge storage of storage capacitors because the absolute value of the threshold voltage (VT) of the cell transfer gate device is larger. Precharging the bitlines is achieved by equalizing the two bitlines, each charged to VDD and .vertline.VTP.vertline., respectively. One node of the sense amplifier retains a full VDD swing and is conveniently connected to the DATA bus. The sense amplifier bitline swing is limited to a swing of VDD-.vertline.VTP.vertline.

Abstract: An improved motive structure for transporting workpieces (wafers, chip, packages, etc.) between processing stations or tools in a manufacturing operation. The structure includes a first circular crankshaft assembly connected to center axles disposed at right angles to the transport motion. A second such crankshaft assembly is located some distance along the path of motion. Three driverods are connected between the first and second crankshaft assemblies, each affixed 120.degree. apart on the circular crankshafts so that each driverod is moved upward, then forward along the transport direction, then downward and backward to its original position as the crankshafts go through a complete 360.degree. rotation. The structure is disposed beneath transport rails which hold movable containers for holding the workpieces. As a driverod moves up and forward, it contacts a spring-loaded element on the movable container and drives it forward by friction contact.

Abstract: User-machine interaction through a touch input display screen is enhanced through the use of surface coding in the form of stylus diameter or reflectivity peripheral surface features that are sensed in optical sensing apparatus.

Abstract: A vertical DRAM cell using VMOS transistors and trench capacitors and the fabrication process therefor. A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination is provided wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate connected to a word line, its drain connected to a bit line, and its source connected to a storage capacitor. More particularly, the storage capacitance node is connected to the source of the V-groove access device through a conducting bridge. The gate of the V-groove access device is connected to the polysilicon word line and the drain is a diffused region which also serves as the bit line of the cell. An epitaxial layer is grown over a combination of single crystalline material and oxide.

Abstract: This die-shaped coarse-approach positioning device is particularly suited for the sample holder of a scanning tunneling microscope or the like. It comprises two blocks (21, 23), one (21) stationary, the other tiltable with respect to the stationary one. The blocks (21, 23) are connected on one side by a spring-like sheet metal (20). The tiltable block (23) can be moved, and with it the sample (33), by turning a screw (28) which presses down onto an elastic pad (30). The tilting of the tiltable block (23) occurs against the effect of the sheet metal (20) until the block (23) touches down onto a wedge (39) insertable in the gap (24) between the blocks (21, 23), and consisting of an elastic material, however, having a spring constant much higher than the effective spring constant of the sheet metal (20). In the application shown, the sample can be lowered onto a tunnel tip (34) attached to a fine-approach positioning device (35).

Abstract: The location of an object in a work area is established by sweeping a single light beam over the area and employing in coordinate calculations the rotational arc of the light source, and the serial events of the light variation when the beam is reflected from a mirror positioned on the opposite periphery intersects the object and the light variation when the beam directly intersects the object.

Abstract: A document scan apparatus in which the position of a document support table relative to an optical system is detected during the relative movement between the document support platen and the optical system. A reference position marker is mounted on the document support table which directly reflects a light from a document illumination light source into an optical sensor array or a CCD sensor array through a mirror and a lens for causing the CCD sensor array to operate in a saturated range to generate a higher output signal level than an expected highest signal level of the CCD sensor array in the document scan operation; and by setting a threshold level of a comparator circuit to a high level which is exceeded by the higher output signal level of the CCD sensor array. The reference position marker is positioned within the field of view of the CCD sensor array for sensing the image of the document, so that the CCD sensor array sensing the document image also senses the reference position marker.

Abstract: A coherent laser beam having a possibly non-uniform spatial intensity distribution is transformed into an incoherent light beam having a substantially uniform spatial intensity distribution by homogenizing the laser beam with a light tunnel (a transparent light passageway having flat internally reflective side surfaces). It has been determined that when the cross-section of the tunnel is a polygon (as preferred) and the sides of the tunnel are all parallel to the axis of the tunnel (as preferred), the laser light at the exit of the light tunnel (or alternatively at any image plane with respect thereto) will have a substantially uniform intensity distribution and will be incoherent only when the aspect ratio of the tunnel (length divided by width) equals or exceeds the contangent of the input beam divergence angle .theta. and whenW.sub.min =L.sub.coh (R+(1+R.sup.2).sup.1/2)>2RL.sub.coh,where W.sub.min is the minimum required width for the light tunnel, L.sub.

Abstract: The calibration of a force sensing type data input device through the use of at least one correction developed by minimization of differences between an actual location of a pattern of test forces and a calculated location of the test forces where the calculation is on the basis of the effect of the test forces on the equilibrium of the device.

Abstract: A process for fabricating a bipolar transistor structure having device and isolation regions fully self-aligned. The transistor is fabricated using a process wherein collector base and emitter layers are sequentially formed on a semiconductor substrate by a molecular beam epitaxy technique. The emitter layer is covered by insulation layers and a photoresist layer is then formed on the insulation layer. The photoresist layer is masked, exposed and developed to provide a pattern which is used as an etch mask to form both the device emitter area and isolation areas. The isolation areas, the emitter region and the base and collector regions are therefore formed.

Abstract: A magnetic recording disk is formed on a rigid aluminum substrate coated with a polymeric dielectric layer. A thin film metallic position-indicating track is applied to the upper surface of the dielectric layer. The dielectric material is coated with a magnetic recording medium. A thin film of aluminum forms the patterned capacitive and optically reflective track. The dielectric layer is composed of a very similar material to the matrix material in the magnetic recording medium.The disk can be flexible or floppy and it is not necessary to have the extra dielectric layer in such a case, where the substrate is a dielectric.