Patents Represented by Attorney John J. Tomaszewski
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Patent number: 6255179Abstract: A method of preparing silicon semiconductor surfaces prior to metal silicide formation. In particular, it teaches a method of treating about 10 to about 200 Å of a surface of the silicon with a plasma source after activating the source and drain regions, prior to an HF etch and deposition of a metal for silicide formation. Discontinuities in the metal silicide formed on narrow polysilicon lines at the point where source and drain regions intersect are surprisingly diminished. This results in more continuous, uniform silicide formation hence the polysilicon lines and the source and drain regions have substantially lower resistance.Type: GrantFiled: August 4, 1999Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: Marc W. Cantell, Kenneth Giewont, Jerome B. Lasky, Kirk D. Peterson
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Patent number: 6253986Abstract: A solder preform is provided for forming interconnections between multilayer ceramic substrates comprising an upper layer and lower layer of solder separated by an intermediate layer of a material which is wettable by solder and which does not melt at the temperatures used to reflow the solder and form the connections. The solder preform is used to join the substrates and is particularly useful to simultaneously electrically interconnect the substrates and to form a hermetic seal between the substrates being joined.Type: GrantFiled: September 22, 1999Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Patrick A. Coico, Mark G. Courtney, Lewis S. Goldmann, Raymond A. Jackson, William E. Sablinski, Kathleen A. Stalter, Hilton T. Toy, Li Wang
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Patent number: 6235544Abstract: A multilayer thin film structure (MLTF) is provided having no extraneous via-pad connection strap plated metallurgy for defective vias needing removal. The method for making or repairing the MLTF comprises determining interconnection defects in the MLTF at a thin film layer adjacent to the top metal layer of the structure, applying a top surface dielectric layer and forming vias in the layer, applying a metal conducting layer and removing the metal conducting layer for via-pad connection straps of defective vias and at the intersection of XY lines used in the repair, defining the top surface metallization including a series of orthogonal X conductor repair lines and Y conductor repair lines using a photoresist and lithography and then using a phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization using additive or subtractive metallization techniques.Type: GrantFiled: April 20, 1999Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Peter A. Franklin, Charles J. Hendricks, Richard P. Surprenant, Stephen J. Tirch, III, Thomas A. Wassick, James P. Wood
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Patent number: 6232667Abstract: An electronic device is provided comprising a stacked integrated circuit chip assembly wherein the top chip of the assembly is solder connected to the surface of an interconnection substrate with the other chips of the assembly being enclosed in a cavity in the interconnection substrate wherein the cavity and electrical connections of the assembly and between the substrate and top chip are sealed by supplying an encapsulant to the cavity through a through opening in the substrate which communicates with the cavity.Type: GrantFiled: June 29, 1999Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Eric B. Hultmark, Brian C. Noble
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Patent number: 6223636Abstract: A gang-punch pin apparatus for punching selected hole patterns in thin sheet materials such as greensheets is provided. The gang-punch pin apparatus uses program plates in the punch apparatus which plates are positioned intermediate the non-punching end of the punch pins and a clearance plate wherein punch pins not used for punching a particular layer of the MLC are retracted into during punching. At the other punch pin locations, the punch pins, upon activation of the punch apparatus by compressing an expandable chamber, usually by application of a force on the punch apparatus, are extended through the lower portion of the punch apparatus to form vias in a greensheet. A die apparatus is also provided for use with the punch assembly to form the vias and to remove the punched material (slugs) from the die apparatus. The gang punch-pin may be shorter than conventional pins and be made at a low cost because of the thin sheet metal plates preferably used to make the component parts of the punch and die apparatus.Type: GrantFiled: August 3, 1998Date of Patent: May 1, 2001Assignee: International Business Machines CorporationInventors: Mark J. LaPlante, James G. Balz, Ferdinand D. DiMaria, John U. Knickerbocker, David C. Long, Thomas Weiss, Robert P. Westerfield, Jr.
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Patent number: 6221269Abstract: A method is provided for etching and removing extraneous molybdenum or debris on ceramic substrates such as semiconductor devices and also for molybdenum etching in the fabrication of molybdenum photomasks. The method employs a multi-step process using an acidic aqueous solution of a ferric salt to remove (etch) the molybdenum debris followed by contacting the treated substrate with an organic quaternary ammonium hydroxide to remove any molybdenum black oxides which may have formed on the exposed surface of treated molybdenum features in ceramic substrates. The method is environmentally safe and the waste solutions may be easily waste treated for example by precipitating the ferric salts as ferric hydroxide and removing anions such as sulfate by precipitation with lime. The method replaces the currently used method of employing ferricyanide salts which create serious hazardous waste disposal and environmental problems.Type: GrantFiled: January 19, 1999Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Krishna G. Sachdev, Umar M. Ahmad, Hsing H. Chen, Lawrence D. David, Charles H. Perry, Donald R. Wall
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Patent number: 6207330Abstract: Exposure masks and inspection masks for use in the electronics field may be made using laser beams wherein the mask comprises a substrate which is substantially unaffected by exposure to the laser beam and an opaque pattern forming layer on the substrate, which pattern forming layer absorbs the laser beam and is selectively etched when exposed to the laser beam. A preferred mask has an overcoat transparent layer. A cavity inspection mask is provided having a series of openings in the form of lines formed in the opaque pattern forming layer, the lines bounding the cavity walls, is the mask being used for determining if the cavity is centrally positioned on the substrate and/or that the cavity is of the desired size. Substrates containing identifying masks thereon which cannot be seen by the unaided eye for theft deterrence are also provided.Type: GrantFiled: March 30, 1999Date of Patent: March 27, 2001Assignee: International Business Machines CorporationInventors: James Gregory Balz, Mark William Kapfhammer, Mark Joseph LaPlante, David C. Long
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Patent number: 6196443Abstract: A solder column structure particularly useful for joining electronic components by C-4 interconnection is provided comprising a solder column attached at one end to one of the substrates being joined and having a layer of indium at the other end. During reflow, to join the other substrate, the indium melts with part of the solder column forming a Pb—Sn—In ternary alloy joint having enhanced fatigue resistance. A method for using the solder column to make electronic component assemblies and electronic component assemblies made using the method and solder column are also provided.Type: GrantFiled: July 16, 1998Date of Patent: March 6, 2001Assignee: International Business Machines CorporationInventor: Giulio DiGiacomo
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Patent number: 6194085Abstract: A coating material used in the fabrication of electronic components such as a metallized paste is provided comprising a material to be coated on the electronic component substrate and an identifying component which identifying component can be identified and which identifying component identifies the coating material. Optical dyes visible to the eye can be used as the identifying component with a preferred dye being a UV fluorescent dye which is colorless under visible light and visible under UV light. A process for making an electronic component using the coating materials of the invention and electronic components made using the coating material are also provided.Type: GrantFiled: September 27, 1997Date of Patent: February 27, 2001Assignee: International Business Machines CorporationInventors: Benjamin V. Fasano, James N. Humenik, David C. Long, Cynthia J. Calli
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Patent number: 6191085Abstract: A method is provided for treating a plurality of semiconductor substrates using the same aqueous SC-1 solution which solution removes and/or inhibits contamination of the semiconductor surfaces by metallic ions present in the solution or on the substrate surface comprising a basic solution containing hydrogen peroxide and an oxidation-resistant chelating additive such as CDTA in an amount effective to provide the desired treatment results. The SC-1 solution may be the conventional 5:1:1 (water:NH4OH:H2O2) solution or a dilute solution such as a 5:x:1 to 200:x:l solution wherein x is 0.025 to 2.Type: GrantFiled: May 10, 1999Date of Patent: February 20, 2001Assignee: International Business Machines CorporationInventors: Emanuel I. Cooper, Scott A. Estes, Glenn W. Gale, Rangarajan Jagannathan, Harald F. Okorn-Schmidt, David L. Rath
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Patent number: 6182884Abstract: A nozzle is provided for the reworking of printed circuit boards with CBGA and CCGA solder containing chips comprising a housing having an internal hot gas chamber and configured to hold at the lower end of the nozzle a chip to be attached to the printed circuit board. The nozzle is provided with a support member and resilient means on the lower surface thereof which resilient means contacts the upper surface of the chip when the chip is placed in the nozzle. When a vacuum is applied to the nozzle the chip is held against the resilient means and compresses the resilient means so that the lower portion of the solder array is below the lower end of the nozzle. When the nozzle is then placed against a printed circuit board, the resilient means provides a pressure force against the chip and the printed circuit board which enables rework of the printed circuit board even though the printed circuit board may be warped.Type: GrantFiled: December 10, 1998Date of Patent: February 6, 2001Assignee: International Business Machines CorporationInventors: Wai Mon Ma, James J. Petrone
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Patent number: 6180953Abstract: A method and apparatus for repairing black dot defects connected to a circuit pattern in photomasks such as a photomask having a patterned chromium film on a glass substrate comprises using an energy source in the form of an energy beam to first sever the connected black dot defect from the chrome pattern forming a space between the defect and the chrome pattern. The remaining severed black dot defect is then removed using the same or different energy beam to remove the remainder of the chrome defect. An apparatus for removing black dot defects and photomasks produced by the method and apparatus of the invention are also provided.Type: GrantFiled: August 26, 1998Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventor: Jacek Smolinski
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Patent number: 6178082Abstract: A multilayer ceramic substrate having a thin film structure containing capacitor connected thereto is provided as an interposer capacitor, the capacitor employing platinum as the bottom electrode of the capacitor. In a preferred capacitor, a dielectric material such as barium titanate is used as the dielectric material between the capacitor electrodes. The fabrication of the interposer capacitor requires an in-situ or post deposition high temperature anneal and the use of such dielectrics requires heating of the capacitor structure in a non-reducing atmosphere. A layer of a high temperature, thin film diffusion barrier such as TaSiN on the lower platinum electrode between the electrode and underlying multilayer ceramic substrate prevents or minimizes oxidization of the metallization of the multilayer ceramic substrate to which the thin film structure is connected during the fabrication process.Type: GrantFiled: February 26, 1998Date of Patent: January 23, 2001Assignee: International Business Machines CorporationInventors: Mukta S. Farooq, David E. Kotecki, Robert A. Rita, Stephen M. Rossnagel
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Patent number: 5293924Abstract: A method is disclosed for improving the continuous casting process for making copper by using a probe and analyzer which measures the gases present in the molten copper and controls the process based on the analyzer results.Type: GrantFiled: February 10, 1993Date of Patent: March 15, 1994Assignee: ASARCO IncorporatedInventors: John R. Hugens, Jr., Stephen L. Ferrel, Gary L. Spence
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Patent number: 5279644Abstract: A new environmentally safe fire refining precious metal assay method is provided wherein bismuth oxide is used with a special flux composition as the precious metal collector and the cupelling procedure is performed in a controlled temperature range.Type: GrantFiled: February 18, 1993Date of Patent: January 18, 1994Assignee: ASARCO IncorporatedInventor: David W. Francisco
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Patent number: 5242571Abstract: A method and apparatus are disclosed for producing copper wire by electrolytically engrossing a copper starting wire. Basically the invention utilizes an electrolytic tank employing a pair or pairs of shafts positioned externally of the tank upon which a minimum of one but generally at least two starting wires are transported on each pair for transfer of the wires through the tank. Multiple tanks, e.g., 10 to 1000 or more, may be used in a single facility for refining or electrowinning processes depending on the quantity of copper wire desired to be produced.Type: GrantFiled: October 26, 1992Date of Patent: September 7, 1993Assignee: ASARCO IncorporatedInventors: Carlos E. R. Sein, William J. Borzick
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Patent number: 5240494Abstract: A method is disclosed for melting copper without incorporating unwanted oxygen and/or hydrogen into the copper by effectively controlling the burners used to melt the copper within desired fuel/air ratio operating limits by employing a special fuel/air mixture sampling and control system.Type: GrantFiled: April 25, 1991Date of Patent: August 31, 1993Assignee: ASARCO IncorporatedInventors: Jim D. Williams, Darrell W. Breitling
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Patent number: 5234492Abstract: An improved process for deleading debismuthized dross is provided wherein the upgraded dross is treated by cupellation to form a slag until the level of bismuth in the upgraded dross reaches about 45% by weight. After cupellation, the partially deleaded upgraded dross may be treated by conventional means such as halogenation to provide a substantially pure bismuth product.Type: GrantFiled: April 14, 1992Date of Patent: August 10, 1993Assignee: ASARCO IncorporatedInventors: Funsho K. Ojebuoboh, Stephen A. Blaskovich
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Patent number: 5201657Abstract: Dental prostheses and a method for manufacturing dental prostheses is disclosed wherein the prosthesis formed requires substantially no bite adjustment by the dentist. This is accomplished by adjusting the height of the prosthesis die relative to the height of the other teeth when the prosthesis is being formed in a device such as an articulator.Type: GrantFiled: February 25, 1992Date of Patent: April 13, 1993Inventor: Theodore J. Koukos
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Patent number: RE34664Abstract: The invention relates to a method and apparatus for electrolytic refining of copper and the production of copper wires for electrical purposes on a continual basis which produces round copper wires directly from impure copper anodes and to treat such wires in order to impart the desired characteristics as electrical conductors. The apparatus handles copper anodes of customary size refining them at normal current densities of less than 55 amps/foot.sup.2 onto starting wires of adequate tensile strength which is done continuously, the wire being provided to an electrolytic bath and, after withdrawal from the bath, the wires are finished by drawing and annealing.Type: GrantFiled: December 23, 1991Date of Patent: July 19, 1994Assignee: ASARCO IncorporatedInventor: Carlos E. Roggero Sein