Abstract: An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.

Abstract: An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first and second bits in a received stream and to provide first and second sign bits. The second equalizer logic can run concurrently and can be connected in parallel relative to the first equalizer logic. The second equalizer logic can include a low and high sign bit pipelines providing first and second conditional sign bits by assuming a low and high sign bits, respectively, for a first bits being concurrently processed by the first equalizer logic and a sign bit selection element to select between the first and second conditional sign bits based on the sign bit outcome of the first equalizer logic. The first and second pipelines compensate bits using compensation weights chosen using most recent first and second conditional sign bits and sign bit outcome.

Abstract: A system comprising converter logic that introduces noise to a signal. The system also comprises amplifier logic that reduces a sound pressure associated with the noise by amplifying the signal prior to providing the signal to the converter logic and de-amplifying the signal after providing the signal to the converter logic.

Abstract: A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.

Abstract: An integrated circuit (200) includes a semiconductor memory device (202) operative for determining match between received search data and stored data in a plurality of ternary content addressable memory (TCAM) bitcells (100). The plurality of TCAM bitcells (100) each include bit storage including a pair of memory cells (102-0, 102-1) for holding stored data. The TCAM bitcells (100) also include bit comparison circuitry (104) operative for comparing between the stored data and search data on a search line coupled to the TCAM bitcell, wherein the bit comparison circuitry includes a static logic gate operable to provide a match output signal exclusive of a pulsed input. Match circuitry (205) is coupled to receive the match output signal (108) from the plurality of TCAM bitcells (100) for determining whether a match is present for a given search word.

Abstract: Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.

Abstract: A data receiver has a clock recovery and data sampling circuit. This has a fixed local oscillator for timing the data samples. A phase interpolator adjusts the phase of the clock signal in response to an early late detector which samples the waveform at the expected position of the edges. A further correction to the sampling position is made in response to the recent history of the data received. The correction is modelled on predictable jitter, for example, that in a transmitter caused by changes in data causing the supply voltage to drop.

Abstract: According to various illustrative embodiments, an apparatus, system, and method for automatically saving and restoring pad configuration registers implemented in a core power domain are described. In one aspect, the apparatus comprises a save and restore logic component implemented in the core power domain and coupled to the pad configuration registers. The apparatus also comprises a memory instantiated in an always-on power domain and coupled to the save and restore logic component, the save and restore logic component implemented in the core power domain to automatically save the pad configuration registers in the memory in a pad configuration save process before a power supply to the core power domain is switched off and to automatically restore the pad configuration registers from the memory in a pad configuration restore process after the power supply to the core power domain is switched on.

Abstract: Various apparatuses and methods for amplifying an FM signal in a segmented linear power amplifier are disclosed herein. For example, some embodiments provide an apparatus including a signal input, a signal output, and an output driver connected between the signal input and the signal output. The output driver includes a number of driver segments connected in parallel, each having an input connected to the signal input and each having an output. The output driver also includes a number of series capacitors, each associated with one of the driver segments. The series capacitors are each connected between the output of its associated driver segment and the signal output. The output driver also includes a number of shunt capacitors, each associated with one of the driver segments having an associated series capacitor. The shunt capacitors are each connected between the output of their associated driver segment and a ground.

Abstract: An embodiment of the invention provides a single-ended polar transmitting circuit. The single-ended polar transmitting circuit comprises a DAC, a differential-to-single-ended converter, a GmC filter and a load. The GmC filter comprises two gain stages, two filters, two switching devices, a translinear loop and a current mirror. When a second clock signal is high, a first current is conducted through the load, a second switching device and a second gain stage. When a first clock signal is high, a second current is conducted through a first switching device and the second gain stage. The first gain stage has a transconductance Gm1 and the second gain stage has a transconductance Gm2. The bandwidth of the GmC filter is approximately equal to the square root of the quantity (Gm1*Gm2)/(C1*C2). The bandwidth of the GmC filter is substantially a constant value.

Abstract: Within a wireless network, uplink control information (UCI) transmitted by user equipment is received by a base station. The UCI includes a least two elements, a first set of symbols produced using a first information element and a second set of symbols produced using a second information element. At least a first metric is produced using the first set and the second set of received symbols. The first information element may then be detected using the first metric.

Abstract: A power control loop includes a feed forward unit 301 coupled to a data source, the feed forward unit 301 processes a signal for transmission, a feedback unit 302 coupled to the feed forward unit 301, the feedback unit 302 generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit 301, a closed loop power control unit 303 coupled to the feedback unit 302 and to the feed forward unit 301, the closed loop power control unit 303 generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source, and a ramp path power control unit 304 coupled to the data source, the ramp path power control unit 304 generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: A system comprising audio logic adapted to convert captured sound into an audio signal. The system also comprises transmission logic which causes noise to be added to the audio signal. The system further comprises processing logic adapted to at least partially remove the noise from the audio signal by subtracting a noise waveform from the audio signal to produce a result signal. The processing logic generates the noise waveform using power level information associated with the transmission logic. The transmission logic transmits the result signal to another electronic device.

Abstract: A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the cell. The NodeB transmits a specific SRI subframe offset and an index value to the particular UE within the cell. The specific SRI subframe offset and the index value enable the UE to determine a unique combination of cyclic shift, RS orthogonal cover, data orthogonal cover, and resource block number for the UE to use as a unique physical resource for an SRI in the physical uplink control channel (PUCCH).

Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

Abstract: Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data.

Abstract: The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.

Abstract: Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.

Abstract: A dual-signal wireless transceiver is provided, comprising: a first wireless transceiver circuit configured to transmit and receive first signals using a first protocol; a second wireless transceiver circuit configured to transmit and receive second signals using a second protocol; and a control circuit configured to generate control signals to control operation of the first and second wireless transceiver circuits, wherein the first wireless transceiver circuit is configured to disable second transmission operations by the second wireless transceiver during first transmission operations by the first wireless transceiver circuit through the use of a shutdown signal. In this method, the second protocol allows the second wireless transceiver to retransmit first signals whose transmission was disabled by the shutdown signal. Furthermore, the second protocol is a Bluetooth protocol, and the first protocol is a wireless protocol other than the Bluetooth protocol.