Abstract: After multilayer conductive stacks are defined in a semiconductor processing sequence, rinsing with a dilute solution of surfactants is performed to remove halogen residues which may ultimately contribute to subsequent undesirable corrosion of the stack.

Abstract: A method of depositing a material upon a substrate is disclosed. A material, such as photoresist, is deposited upon a substrate such as a semiconductor wafer by spinning the substrate and commencing deposition at the edge of the wafer and moving inward in a spiral pattern. The method produces a more uniform coating than hitherto available.

Abstract: An integrated circuit, illustratively an SRAM, having a low resistance path between an access transistor and a pull down transistor is disclosed. Connection for the cell load to the node between the access transistor and pull down transistor is made outside the defined current path.

Abstract: A semiconductor integrated circuit, and process for its manufacture, are disclosed which contains both n.sup.+ and p.sup.+ gates that do not pose a risk of dopant interdiffusion. Both n.sup.+ and p.sup.+ gates may be fabricated by conventional means. The gate structures are severed over the tub boundaries. A titanium nitride interconnective layer is deposited and patterned over the gates. The interconnective layer preserves connectivity between the n.sup.+ and p.sup.+ gates without risk of deleterious dopant interdiffusion.

Abstract: A signal processor with an embedded Viterbi co-processor is disclosed. The Viterbi branch metric unit contains embedded metric units which calculate either Euclidean or Manhattan metrics for MLSE or deconvolution operations.

Abstract: A method of forming a planarized or smoothed dielectric or other material layer upon a partially fabricated intergrated circuit is disclosed. Conventional planarization techniques involve deposition of a dielectric or other material layer followed by anisotropic etchback. Unfortunately, some commercial equipment tends to etch the center of the wafer faster than the edges. The disclosed process forms a layer which is thicker in the central region than the edge region. Thus, when the disclosed process is followed by a conventional etchback, a planar dielectric or other material layer over the entire wafer is formed. Other aspects of the invention include processes and apparatus for producing smooth deposition and etching by control of the impedance of the etching and/or chemical precursor gases.

Abstract: A method for forming an anti-reflective coating useful in the fabrication of integrated circuits is discussed. Applicants have found that preheating semiconductor wafers prior to the application of amorphous silicon anti-reflective coatings tends to reduce undesirable particulates which may attach to the wafer. The process is illustratively performed in a Varian 3180 machine having four stations. Illustratively, the wafer may be preheated between 70.degree. C. and 175.degree. C. prior to and during the sputter deposition of an amorphous silicon anti-reflective coating.

Abstract: A method for etching metal conductors and stacks of conductors is disclosed. A doped silicon dioxide layer is deposited upon a metal or stack of conductive layers to be etched. A silicon dioxide layer is doped with phosphorous. Next, the silicon dioxide layer is partially etched and the photoresist removed. Subsequent etching utilizes the raised feature created in the silicon dioxide layer as a mask to etch the underlying metal or stack of conductors.

Abstract: A method for forming transistors having sublithographic features, for example, gates, is disclosed. A patterned hardmask (formed, for example from PETEOS) is created overlying oxide and polysilicon layers. The dimensions of the hardmask are reduced by isotropic etching. The reduced-dimension hardmask is used with an anisotropic etching process to define a reduced-dimension feature such as a gate.

Abstract: A method of fabricating integrated circuits is disclosed. A layer of doped silicon dioxide is deposited over a partially fabricated integrated circuit. The doped silicon dioxide is heated to permit it to attract sodium ions. After the doped silicon dioxide has been heated, it is removed by an etching process which exhibits great selectivity to the remaining underlying portion of the integrated circuit.

Abstract: The addition of ligands for chelating Group I and Group II ions to organic solvents used for photoresist removal and etched conductor cleaning enhances the shelf life of these solvents. Furthermore, mobile ion contamination of integrated circuits processed with ligands modified organic solvents is reduced.

Abstract: A method of semiconductor integrated circuit fabrication including a technique for forming punch-through control implants is disclosed. After gate formation, a dielectric is formed which covers the gate and exposed portions of a semiconductor substrate. The dielectric is formed by a process which makes that portion of the dielectric adjacent the gate sidewalls more vulnerable to wet etching than those portions of the dielectric which are adjacent the top of the gate and the exposed substrate. The dielectric is then subsequently etched to form channels adjacent the gate which exposed the substrate and served to collimate an ion implantation beam. The remaining portions of the dielectric may then be stripped away and conventional procedures employed to form source and drain. Illustratively, the dielectric is formed from TEOS to which NF.sub.3 is added during the deposition process. The addition of NF.sub.

Abstract: A method for forming a twin tub semiconductor integrated circuit is disclosed. A portion of a semiconductor substrate is masked by oxide, nitride and photoresist. P-type dopant is directed towards the other portion of the substrate. Subsequently, the photoresist is removed and a protective oxide is grown over the p-tub, thereby driving the dopant into the substrate. Next, an n-type ion implantation is performed to create the n-tub. The n-type ions are directed at the substrate at an angle which is away from normal incidence. The angular direction of the n-type dopants permits the use of smaller screen oxides over the n-tub and smaller protective oxides over the already-formed p-tub. When all of the protective oxides have been removed, the inventive technique provides a twin tub substrate having a comparatively smooth upper surface.

Abstract: A method of semiconductor integrated circuit fabrication which provides a tapered window and a smoothed dielectric. A trench is made by etching through patterned photoresist into a dielectric. Then the corners of the trench are smoothed by thermal flow. Next the trench is etched downward by RIE blanket etchback. A window with tapered sides is thereby opened to the substrate and the dielectric is simultaneously smoothed.

Abstract: A method of depositing a material upon a substrate is disclosed. A material, such as photoresist, is deposited upon a substrate such as a semiconductor wafer by spinning the substrate and commencing deposition at the edge of the wafer and moving inward in a spiral pattern. The method produces a more uniform coating than hitherto available.

Abstract: A programmable function unit (PFU) well adapted for use in a field programmable gate array (FPGA) is disclosed. The PFU utilizes programmable fast ripple logic. A programmable generator and/or a programmable propagator are implemented in look up tables in each PFU block. A multiplexer under control of the propagator determines whether to transmit the carry in from the previous block or to transmit the generator signal.

Abstract: A method of forming a planarized or smoothed dielectric or other material layer upon a partially fabricated integrated circuit is disclosed. Conventional planarization techniques involve deposition of a dielectric or other material layer followed by anisotropic etchback. Unfortunately, some commercial equipment tends to etch the center of the wafer faster than the edges. The disclosed process forms a layer which is thicker in the central region than the edge region. Thus, when the disclosed process is followed by a conventional etchback, a planar dielectric or other material layer over the entire wafer is formed. Other aspects of the invention include processes and apparatus for producing smooth deposition and etching by control of the impedance of the etching and/or chemical precursor gases.

Abstract: A method to achieve good stepper focus and exposure over an entire wafer for a particular mask level before the start of a product run is described. This method can also be used to produce a characterization of lens field curvature (i.e., a surface of optimum focus across the lens) and to characterize lens astigmatism, defocus sensitivity, relative resolution, and other characteristics, and to check the stepper for optical column tilt. The process prevents the complexities of resist development from affecting determination of focus. The process involves forming an array of latent images in a resist and examining the scattered light from the edges of the latent images. Analysis of the scattered light quickly provides information on correct exposure and focus together with lens characteristics over the printing field.

Abstract: An integrated circuit, illustratively an SRAM, with pull down gates symmetrically positioned with respect to the ground line is disclosed. The symmetric positioning helps to insure cell stability.

Abstract: A method of forming an interlevel dielectric suitable for use with semiconductor integrated circuits is disclosed. The dielectric illustratively includes a triple layer sandwich of ozone-TEOS formed between two layers of plasma-enhanced TEOS. The dielectric is capable of filling high-aspect ratio trenches between runners. The ozone-TEOS is formed at a high pressure (approximately 90 Torr) to reduce hydrogen absorption. The reduced-hydrogen content ozone-TEOS is less susceptible to moisture formation and, therefore, presents less risk of degrading subsequently formed aluminum runners.