Patents Represented by Attorney, Agent or Law Firm John T. Rehberg
-
Patent number: 5045486Abstract: A method of forming a transistor is disclosed. Conventional fabrication techniques direct an ion implantation beam toward a substrate upon which a gate has already been formed. If the gate stack is too low relative to the incident beam energy, the dopant species may channel thorugh the gate stack, adversely affecting transistor performance. The present invention prevents channeling through this gate by covering the gate with a protective layer before ion implantation.Type: GrantFiled: June 26, 1990Date of Patent: September 3, 1991Assignee: AT&T Bell LaboratoriesInventors: Sailesh Chittipeddi, William T. Cochran, Michael J. Kelly
-
Patent number: 4952524Abstract: A trench which provides electrical isolation between transistors on an integrated circuit substrate is described. The trench is lined with a diffusion barrier, typically a thermal oxide followed by a thermal stress relief layer, typically formed from TEOS. Then a filler material, typically BPTEOS, is deposited to fill the trench and cover the upper surface of the wafer. The filler material is heated to make it flow. Next the outer surface of the flowed filler material is next subjected to an etch-back which makes the top surface of the filled trench protrude slightly above the upper surface of the substrate. The resulting trench contains the diffusion barrier layer, the thermal stress relief layer, and the filler material. The filler material and the thermal stress relief layer will soften during subsequent heat treatments of the wafer, thus relieving thermal stresses, and preventing the occurrence of defects and dislocations within the wafer.Type: GrantFiled: May 5, 1989Date of Patent: August 28, 1990Assignee: AT&T Bell LaboratoriesInventors: Kuo-Hua Lee, Chih-Yuan Lu
-
Patent number: 4950977Abstract: Mobile ion concentrations are measured in thick and disordered oxides by heating to a temperature greater than about 250.degree. C.; using a triangular voltage sweep-like method with applied voltages substantially greater than normally used heretofore; and observing peak displacement currents at voltages, e.g., greater than 60 volts, substantially greater than zero volts.Type: GrantFiled: December 21, 1988Date of Patent: August 21, 1990Assignee: AT&T Bell LaboratoriesInventors: Agustin M. Garcia, Cris W. Lawrence, Morgan J. Thoma
-
Patent number: 4922311Abstract: A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. There is a conducting layer, termed a window pad layer, over portions of these regions. Because of the insulating top layer and sidewall spacers on the gate, the window may be misaligned with respect to the source and drain regions, and maybe even closer to the gate than are these regions, but electrical contacts to these regions are still obtained. The window pad layer may also be used as sublevel interconnect.Type: GrantFiled: April 11, 1989Date of Patent: May 1, 1990Assignee: American Telephone and Telegraph CompanyInventors: Kuo-Hua Lee, Chih-Yuan Lu, David S. Yaney
-
Patent number: 4919748Abstract: A method for etching metal layers including aluminum to create tapered sidewalls is disclosed. The method features the use of trifluoromethane and chlorine in controlled amounts to create a tapered metal layer profile.Type: GrantFiled: June 30, 1989Date of Patent: April 24, 1990Assignee: AT&T Bell LaboratoriesInventors: Craig N. Bredbenner, Troy A. Giniecki, Nur Selamoglu, Hans J. Stocker
-
Patent number: 4900947Abstract: A Marx high voltage generator with a fast rise time. Photoconductive semiconductor switches are sequentially triggered by a single laser via fiber optic bundles of different lengths. The switches serve to series connect a group of charged capacitors. Output is taken from the last capacitor which receives the voltage accumulated on all of the previous capacitors. Proper timing of the activation of each switch produces a fast rise time.Type: GrantFiled: May 2, 1988Date of Patent: February 13, 1990Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Maurice Weiner, Anderson H. Kim, Lawrence J. Bovino
-
Patent number: 4844776Abstract: A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. The window pad layer may also be used as a sublevel interconnect.Type: GrantFiled: December 4, 1987Date of Patent: July 4, 1989Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventors: Kuo-Hua Lee, Chih-Yuan Lu, David S. Yaney
-
Patent number: 4839059Abstract: A linear array of clad truncated magic ring segments. Each segment has an entrance and exit hole in its respective cladding magnets. The individual segments are arranged to provide a periodic permanent magnet structure suitable for use in a wiggler or a twister.Type: GrantFiled: June 23, 1988Date of Patent: June 13, 1989Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Herbert A. Leupold
-
Patent number: 4835585Abstract: The specification describes several forms of trench gate MOS transistors and methods for making them. The structure further includes a pair of sidewall guards on opposing sidewalls to prevent inversion of the sidewalls when the trench gate is turned on.Type: GrantFiled: November 26, 1984Date of Patent: May 30, 1989Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventor: Peter T. Panousis
-
Patent number: 4835584Abstract: The specification describes a new MOS transistor structure in which the source gate and drain are formed within a trench in the semiconductor substrate. The gate width is determined by the depth of the trench and can be increased substantially without increasing the surface area occupied by the transistor. The result is a transistor with exceptionally high gain for a given surface area. Forming the transistor within and over a series of trenches further enhances this effect.Type: GrantFiled: March 16, 1987Date of Patent: May 30, 1989Assignee: American Telephone and Telegraph Company, AT&T Bell LaboratoriesInventor: Loren T. Lancaster
-
Patent number: 4832789Abstract: A self-assigned, self-planarized metallization scheme for multilevel interconnections using self-aligned windows in integrated circuits is described. Trenches are etched into a dielectric and then, using an etch stop layer on top of the dielectric to prevent unwanted etching of the dielectric, self-aligned windows which expose portions of the substrate are etched in the dielectric. Self-aligned windows can also be formed without a mask.Type: GrantFiled: April 8, 1988Date of Patent: May 23, 1989Assignee: American Telephone and Telegrph Company, AT&T Bell LaboratoriesInventors: William T. Cochran, Agustin M. Garcia, Graham W. Hills, Jenn L. Yeh
-
Patent number: 4820688Abstract: Microwave oscillators and amplifiers which utilize a superconducting slow-wave circuit. The slow circuit is made from materials which exhibit superconductivity at relatively high critical temperatures. The slow wave circuit is integral with the device's vacuum housing. Coolant exterior to the vacuum housing maintains the circuit in the superconducting state. The slow-wave circuit, which protrudes into the vacuum housing provides modulation of an electron beam which traverses the interior of the vacuum housing. Output power is ultimately extracted from the slow wave circuit.Type: GrantFiled: November 27, 1987Date of Patent: April 11, 1989Inventor: Louis J. Jasper, Jr.
-
Patent number: 4807013Abstract: Disclosed is an integrated circuit manufacturing technique that relies on the use of polysilicon fillets for overcoming the well known adverse effects of steep sidewalls produced by anisotropic etching processes and undercuts produced by anisotropic etching of multilayers.Type: GrantFiled: April 8, 1987Date of Patent: February 21, 1989Assignee: American Telephone and Telegraph Company AT&T Bell LaboratoriesInventor: Ajit S. Manocha
-
Patent number: 4785232Abstract: A method and apparatus for the contactless, non-destructive measurement of Hall coefficient and resistivity of a piezoelectric semiconductor sample. The material to be tested is formed in a disk which is supported at its edge by a holder. The disc is free to vibrate. Two pairs of electrodes, placed above and below the sample, excite the sample into and beyond piezoelectric resonance. Then a magnetic field is applied to the sample and the sample again driven into and beyond resonance. Comparison between the performance of the disk before and after application of the magnetic field yields data from which Hall coefficient can be determined.Type: GrantFiled: June 5, 1987Date of Patent: November 15, 1988Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Arthur Ballato, Herbert A. Leupold
-
Patent number: 4782309Abstract: A crystal oscillator in a bridge circuit coupled to a differential amplifier. Coordinated adjustment of one or two arms of the bridge permits pulling of the crystal's operating frequency both above and below its series resonant frequency.Type: GrantFiled: June 26, 1987Date of Patent: November 1, 1988Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Albert Benjaminson
-
Patent number: 4767988Abstract: The orientation of a moving platform with respect to a magnetic field is determined by rotating a 3-component vector magnetometer mounted on the platform about at least two axes in the magnetic field. Changes in the signals from the magnetometer are monitored, and the direction of the magnetic field relative to the platform is computed from the signal changes. It is not necessary to know the DC bias of each magnetometer channel or the component of the background magnetic field along each axis of the magnetometer.Type: GrantFiled: June 13, 1986Date of Patent: August 30, 1988Assignee: Her Majesty the Queen in right of Canada, as represented by the Minister of National DefenceInventor: Harold S. Wilson
-
Patent number: 4762735Abstract: An optical waveguide comprises two out-diffused optical waveguide sections an in-diffused optical waveguide section, and two narrow transition region intimately connecting the out-diffused waveguide sections and the in-diffused waveguide section. This waveguide structure can decrease the level of in-plane scattering caused by surface irregularities and reduce the difficulty of coupling light into and out of the waveguide. The structure can be made to perform as a transverse magnetic mode filter and increase the intensity of light focussed into the guide beyond the limits imposed by the optical damage resistance of a strictly in-diffused waveguide.Type: GrantFiled: December 7, 1987Date of Patent: August 9, 1988Assignee: Her Majesty the Queen in Right of Canada, as represented by the Minister of National DefenceInventors: Dennis J. Gregoris, Roger Arsenault, Velimir M. Ristic
-
Patent number: 4761048Abstract: An optical waveguide comprises two out-diffused optical waveguide sections, an in-diffused optical waveguide section, and two narrow transition regions intimately connecting the out-diffused waveguide sections and the in-diffused waveguide section. This waveguide structure can decrease the level of in-plane scattering caused by surface irregularities and reduce the difficulty of coupling light into and out or the waveguide. The structure can be made to perform as a transverse magnetic mode filter and increase the intensity of light focussed into the guide beyond the limits imposed by the optical damage resistance of a strictly in-diffused waveguide.Type: GrantFiled: April 13, 1987Date of Patent: August 2, 1988Assignee: Her Majesty the Queen in right of Canada, as represented by the Minister of National DefenceInventors: Dennis J. Gregoris, Roger Arsenault, Velimir M. Ristic
-
Patent number: 4760769Abstract: A rapid-fire electromagnetic projectile launcher. The invention features parallel disks with gaps in their peripheries. A voltage source is applied to the disks to cause current to flow in opposite directions through the disks, generating a strong repulsive force which is utilized to eject a projectile. A rotator is positioned concentric with the disks to control timing of the repulsive action and facilitate projectile reloading.Type: GrantFiled: April 27, 1987Date of Patent: August 2, 1988Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Louis J. Jasper, Jr.
-
Patent number: H591Abstract: A method of making a permanent magnet magic ring structure. An annular cyder made from a magnetically hard material is uniformly magnetized in a direction perpendicular to its major axis. The cylinder is cut into eight or sixteen or 32 or more segments. Various segments are interchanged with other segments to produce a magic ring which has an intense uniform magnetic field within a central working space.Type: GrantFiled: July 5, 1988Date of Patent: March 7, 1989Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Herbert A. Leupold