Abstract: A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connection between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

Abstract: A method for wet etching disposable spacers in silicon integrated circuits is provided. Illustratively, a pair of spacers is formed over a polysilicon substrate. A second pair of spacers is formed from doped silicon dioxide over the first pair of spacers. Then the second pair of spacers is etched away with NH.sub.4 OH/H.sub.2 O.sub.2, thus providing a means for defining the underlying polysilicon layer, e.g., by etching.

Abstract: A method for forming an anti-reflective coating useful in the fabrication of integrated circuits is discussed. Applicants have found that preheating semiconductor wafers prior to the application of amorphous silicon anti-reflective coatings tends to reduce undesirable particulates which may attach to the wafer. The process is illustratively performed in a Varian 3180 machine having four stations. Illustratively, the wafer may be preheated between 70.degree. C. and 175.degree. C. prior to and during the sputter deposition of an amorphous silicon anti-reflective coating.

Abstract: A method for anisotropically depositing a dielectric from a precursor gas in a reactor is disclosed. The method includes reduced pressure, reduced oxygen/precursor gas flow ratio, increased spacing between shower head and susceptor; and also a susceptor having a diameter greater than the diameter of the wafer.

Abstract: In the manufacture of integrated circuits, a process for forming a dielectric layer such as silicon dioxide which has a high wet etch rate is disclosed. Illustratively, the process is performed with a precursor gas in a plasma reactor with a shower head and a susceptor which supports a wafer. The power density, pressure, susceptor-shower head spacing, and (optionally) temperature are respectively decreased, decreased, increased and decreased to reduce the effectiveness of dissociation of the precursor gas. The resulting film contains impurities which enhance its wet etch rate.

Abstract: A method of forming p.sup.+ transistor gates is disclosed. A polysilicon layer is covered with an amorphous silicide layer which prevents penetration of p-type dopants through the gate oxide. The silicide may be covered by a dielectric which is formed at a temperature low enough to prevent crystallization of the silicide, a p-type dopant species is directed at the silicide layer. Subsequently an anneal is performed at a temperature high enough to cause a substantial amount of the p-type dopant to move to the polysilicon layer.

Abstract: A conductive layer is formed beneath a runner in an integrated circuit. The conductive layer is also formed within vias. The conductive layer preserves electrical connection should the runner separate due, perhaps, to electromigration or stress voiding. The conductive layer also provides protection against various failures or defects which may occur in the runner material within the vias.

Abstract: A method for forming an integrated circuit with a planarized dielectric is disclosed. Runners and gates are covered with a protective dielectric layer. Then a conventional dielectric is deposited and planarized over the entire circuit surface. When windows are opened to runners and to source/drain regions, the protective dielectric helps to slow the etch process over the runner, thus protecting the runner from damage during the extra time required for the etch process to reach the source or drain.

Abstract: A method for forming a dielectric layer in an integrated circuit is disclosed. After a first dielectric layer is formed, a second dielectric layer is formed on top of the first layer. The second layer is formed by reducing precursor gas flow during the initial portion of the deposition process so that the initial film density of the deposited dielectric is higher or equal to the density of the bulk of the first and second dielectric.

Abstract: A method for forming a thin high quality interlevel dielectric is disclosed. The dielectric is produced in a plasma reactor utilizing a precursor gas such as TEOS. Pressure, power, temperature, gas flow, and showerhead spacing are controlled so that a dielectric of TEOS may be deposited at 60-5 .ANG. / sec, thus making formation of thin (800 .ANG.) high quality dielectrics feasible.

Abstract: A method for forming a bipolar transistor is disclosed. An optional thin screen oxide (.apprxeq.150 .ANG.) may be formed upon a substrate over an already-defined collector region. A BF.sub.2 or other implantation is performed through the screen oxide to create the base. The screen oxide is removed and replaced with a patterned high pressure oxide so that the emitter may be defined. The resulting device has a more controllable Gummel number and breakdown voltage.

Abstract: A process for removing both the silicon nitride layer and polysilicon layer in a poly-buffered LOCOS process which utilizes hot phosphoric acid is disclosed.

Abstract: A method of forming a planarized or smoothed dielectric or other material layer upon a partially fabricated integrated circuit is disclosed. Conventional planarization techniques involve deposition of a dielectric or other material layer followed by anisotropic etchback. Unfortunately, some commercial equipment tends to etch the center of the wafer faster than the edges. The disclosed process forms a layer which is thicker in the central region than the edge region. Thus, when the disclosed process is followed by a conventional etchback, a planar dielectric or other material layer over the entire wafer is formed. Other aspects of the invention include processes and apparatus for producing smooth deposition and etching by control of the impedance of the etching and/or chemical precursor gases.

Abstract: Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.

Abstract: A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

Abstract: An integrated circuit and method of fabrication are disclosed. The invention provides an etch-stop layer between a plug formed in a via and an overlying runner. The etch stop layer serves a variety of functions, including protecting the plug during the etching process which defines the runner.

Abstract: A process for the formation of material layers such as amorphous silicon is disclosed. When a precursor gas such as silane is utilized to form amorphous silicon, silicon crystals are often formed on top of the amorphous silicon layer. The crystals are created by the presence of low pressure silane in the reactor at the end of the deposition cycle. Formation of crystals is inhibited by lowering the temperature before silane flow is terminated.

Abstract: Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.

Abstract: In a two-step etching process for making tapered contact openings in a dieletric, a thin layer of a material is interposed to serve as an adhesive between the dielectric and a photoresist layer the thin layer of material is chosen to remain essentially intact during undercut partial etching of the dielectric. As a result of enhanced adhesion, the photoresist layer remains more accurately positioned for subsequent anisotropic etching across the remainder of the thickness of the dielectric.

Abstract: In the manufacture of integrated-circuit devices, patterned features are made on a substrate by etching a deposited layer. The pattern comprises features which are closely spaced, as well as others which are more isolated. Etching is in approximate conformance with a lithographically defined resist pattern which in turn is in approximate conformance with a desired pattern. A processing parameter such as, e.g., resist layer thickness is chosen such that an etched pattern is obtained which approximates a desired pattern more closely than a lithographically defined resist pattern.