Abstract: A method for color conversion applying minimal surface theory to the formation of the volumes in a three-dimensional color cube. Volume center points on the color cube are selected as entries in a color look-up table, and these center points are plotted on the color cube. Spheres centered about each volume center point are created, and the discrete locations in the color cube falling within each sphere are associated with the CLUT entry corresponding to that volume center point. The radii of the spheres are incrementally increased, and the discrete locations falling within the enlarged spheres are associated with the corresponding CLUT entry. As the spheres enlarge they begin to intersect. The intersection of the spheres form planes which divide the discrete locations such that each discrete location is associated with the closest volume center point.

Abstract: The present invention provides an enhanced method and device to inhibit or reduce the rate of restenosis following angioplasty or stent placement. The invention involves placing a balloon tipped catheter in the area treated or opened through balloon angioplasty immediately following angioplasty. The balloon, which can have a dual balloon structure, may be delivered through a guiding catheter and over a guidewire already in place from a balloon angioplasty. A fluid such as a perfluorocarbon may be flowed into the balloon to freeze the tissue adjacent the balloon, this cooling being associated with reduction of restenosis. The catheter may also be used to reduce atrial fibrillation by inserting and inflating the balloon such that an exterior surface of the balloon is in contact with at least a partial circumference of the portion of the pulmonary vein adjacent the left atrium.

Abstract: A memory system comprises a memory, a memory controller and a cache. The memory stores a plurality of data packets, which are associated with a plurality of data types. The memory controller receives requests for data packets from a processing unit and passes requested data packets from the memory to the processing unit. The cache comprises a plurality of independently cached areas. The memory controller passes requested data packets from the memory to the cache. The memory controller passes requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller. The memory controller assigns each independently cached area in the cache to store data packets associated with one item type where an item type may be a texture, thread, task or process. Each independently cached area is associated with a data usage indicator.

Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Abstract: A non-invasive system and process for converting sensory data, e.g., visual, audio, taste, smell or touch, to neural firing time differences in a human brain and using acoustic signals to generate the neural firing time differences. Data related to neural firing time differences, the acoustic signals, and a user's response map may be stored in memory. The user's response map may be used to more accurately map the calculated neural firing time differences to the correct neural locations.

Abstract: The invention provides a method and device for selectively controlling the temperature of a selected organ of a patient for performance of a specified application. The method includes introducing a guide catheter into a blood vessel. The guide catheter may have a soft tip and a retaining flange, and may be used to provide treatments such as administration of thrombolytic drug therapies, stenting procedures, angiographic procedures, etc. A supply tube is provided having a heat transfer element attached to a distal end thereof. The heat transfer element having a plurality of exterior surface irregularities, these surface irregularities having a depth greater than the boundary layer thickness of flow in the feeding artery of the selected organ. The supply tube and heat transfer element may be inserted through the guide catheter to place the heat transfer element in the feeding artery of the selected organ.

Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.

Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced, by providing a bottom frame matrix including a plurality of bottom frame units, each of which unit includes a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit includes a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.

Abstract: A method and apparatus for decoding an input MPEG video stream are provided that includes a core processor with a very large instruction word (VLIW) processor and a co-processor that includes a variable length decoder (VLD) for decoding the MPEG video stream. The input MPEG video stream is organized into macroblocks, wherein each macroblock includes a header for a macroblock that is not decoded, and encoded data for a macroblock whose header is previously decoded by VLD. Thereafter, VLD decodes the encoded video data of a first macroblock whose header has been decoded, and decodes the header of a second (current) macroblock. VLIW then performs motion compensation on a current macroblock based upon reference data of a previously decoded macroblock. VLIW also adds a fake slice start code and fake macroblock data at the end of each picture into the input MPEG video data stream; and utilizes the fake slice start code and fake macroblock data to skip to a next picture.

Abstract: A video projection device includes a cabinet having front and rear sections and a projection tube for projecting a video image. The video projection device also includes a screen located in the front section of the cabinet. The screen has a first surface onto which the video image is projected and a second surface for displaying the video image so that it is observable by a viewer. A mirror is arranged in the cabinet for reflecting light to the first surface of the screen. The mirror is a composite laminate mirror that includes a rigid substrate and a reflective sheet laminated to the rigid substrate. The rigid substrate may be a glass substrate and the reflective sheet may be a flexible plastic sheet. The reflective sheet may have a multilayer construction that includes a metallic film. The reflective sheet may alternatively include a second substrate and at least one thin film layer deposited on the substrate.

Abstract: A method for fabricating a high voltage power MOSFFT having a voltage sustaining region that includes doped columns formed by rapid diffusion. A high voltage semiconductor device having a substrate of a first or second conductivity type, an epitaxial layer of the first conductivity on the substrate, and a voltage sustaining region formed in the epitaxial layer, the voltage sustaining region including a column having a second conductivity type formed along at least outer sidewalls of a filled trench, the column including at least one first diffused region and a second diffused region, the first diffused region being connected by the second region and the second region having a junction depth measured from the trench sidewall that is less than the junction depth of the first region and a third region of a second conductivity type that extends from the surface of the epitaxial layer to intersect at least one of the first and second regions of second conductivity type.

Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.

Abstract: A video projection device includes a cabinet having front and rear sections and a projection tube for projecting a video image. The video projection device also includes a screen located in the front section of the cabinet. The screen has a first surface onto which the video image is projected and a second surface for displaying the video image so that it is observable by a viewer. A mirror is arranged in the cabinet for reflecting light to the first surface of the screen. The mirror is a composite laminate mirror that includes a rigid substrate and a reflective sheet laminated to the rigid substrate. The rigid substrate may be a glass substrate and the reflective sheet may be a flexible plastic sheet. The reflective sheet may have a multilayer construction that includes a metallic film. The reflective sheet may alternatively include a second substrate and at least one thin film layer deposited on the substrate.

Abstract: A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.

Abstract: A trench DMOS transistor structure is provided that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region of the first conductivity type in the body region adjacent to the trench.

Abstract: A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

Abstract: A method and system for enhancing digital video transmission to set-top boxes improves the performance of a hybrid analog and digital video transmission system, for example, an AM-VSB QAM video transmission system, by selecting a digital channel map based on the relative magnitude and frequency locations of CSO and CTB distortions and the analog channel frequency plan. A variable interleaver may also be implemented in the video transmission system to further reduce the CSO and CTB distortions.

Abstract: A non-invasive system and process for projecting sensory data onto the human neural cortex is provided. The system includes a primary transducer array and a secondary transducer array. The primary transducer array acts as a coherent signal source, and the secondary transducer array acts as a controllable diffraction pattern that focuses energy onto the neural cortex in a desired pattern. In addition, the pattern of energy is constructed such that each portion projected into the neural cortex may be individually pulsed at low frequency. This low frequency pulsing is formed by controlling the phase differences between the emitted energy of the elements of primary and secondary transducer arrays.

Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.