Patents Represented by Law Firm Katz & Cotton, LLP
  • Patent number: 5568632
    Abstract: The present invention is an improved method and apparatus for selecting and replacing a block of a set of cache memory. The present invention provides for the weighted random replacement of blocks of cache memory by assigning indices to the memory blocks of a given set of cache memory. One of the assigned indices is then randomly selected by the present invention. The memory block of the given set to which the randomly selected index is assigned is replaced. The indices are assigned such that one or more blocks of the given set of cache memory have a high probability of replacement, whereas the other blocks of the given set of cache memory have significantly lower probabilities of replacement.
    Type: Grant
    Filed: December 17, 1993
    Date of Patent: October 22, 1996
    Assignee: LSI Logic Corporation
    Inventor: S. Craig Nelson
  • Patent number: 5565385
    Abstract: Composite bond pad structure and geometry increases bond pad density and reduces lift-off problems. Bond pad density is increased by laying out certain non-square bond pads which are shaped, sized and oriented such that each bond pad closely conforms to the shape of the contact footprint made therewith by a bond wire or lead frame lead and aligns to the approach angle of the conductive line to which it is connected. Alternating, interleaved, complementary wedge-shaped bond pads are discussed. Bond pad liftoff is reduced by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad and is filled with conductive material.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: October 15, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Dorothy A. Heim
  • Patent number: 5563380
    Abstract: An apparatus and method for mounting and connecting a plurality of integrated circuit chip dice to a printed circuit substrate by means of a small circuit board (such as a Mini-Board) that may be adapted to attach and connect into a plurality of different types of printed circuit board systems. A pattern of conductors that monotonically increases in pitch and width from a central point on a planar structure to the perimeter edge of the structure allows matching of any type of printed circuit board connections. A standard Mini-Board may be fabricated and tested before attaching to an electronic system printed circuit board. Repair and rework is easily facilitated with a minimum amount of damage to a printed circuit board by utilizing the present invention. A plurality of active and passive electronic components may also be attached and connected to the planar structure of the present invention. A hybrid mini-system may be fabricated and tested before connecting it into a system printed circuit board.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: October 8, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch
  • Patent number: 5561086
    Abstract: In cases where there are at least some large gaps between edges of a semiconductor die and the inner ends of package conductors defining a die-receiving area, one or more bond wire support structure are disposed in the gap, thereby causing a long bond wire to behave as two or more shorter bond wires. The bond wires are tacked to a top surface of the support structure by various alternative means. Alternatively, a "jumper" structure having conductive traces of graduated length can be disposed in the die-receiving area between the die and the edges of the die-receiving area, providing an intermediate connection between the die and the leads of the package, thereby permitting short bond wires to be used in lieu of long bond wires.
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: October 1, 1996
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rostoker
  • Patent number: 5557150
    Abstract: A technique for providing partially and fully overmolded semiconductor packages is described which prevents delamination (detachment) of the molding compound from the substrate by allowing the molding compound to flow through holes in the substrate and forming it into rivet-like anchors on the opposite side of the substrate. Various shapes of rivet-like anchors are described. Different embodiments provide for the formation of molded standoffs and locating pins integral to the anchor structures.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: September 17, 1996
    Assignee: LSI Logic Corporation
    Inventors: Patrick Variot, Chok J. Chia
  • Patent number: 5557066
    Abstract: Plastic (or resinous) materials used to package (or support) electronic devices typically have thermal coefficients of expansion exceeding that of the device to be packaged. A "loading" material (agent) having a coefficient of expansion significantly less than the "base" plastic material (molding compound), less than that of the die, and preferably zero or negative over a temperature range of interest, is mixed with the "base" plastic material to produce a plastic molding compound with a lower overall thermal coefficient of expansion. Titanium dioxide, zirconium oxide and silicon are discussed as loading agents. The loading material is mixed into the plastic molding compound in sufficient quantity to ensure that the resulting mixture exhibits an overall thermal coefficient of expansion that is more closely matched to that of the electronic device.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: September 17, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Patent number: 5556549
    Abstract: The present invention relates to a system and method for control and delivery of radio frequency power in plasma process systems. The present invention monitors the power, voltage, current, phase, impedance, harmonic content and direct current bias of the radio frequency energy being delivered to the plasma chamber. In addition, the plasma mode of operation may be controlled by creating either a capacitively or inductively biased radio frequency source impedance. A radio frequency circulator prevents reflected power from the plasma chamber electrode to damage the power source and it further dissipates the reflected power in a termination resistor. The termination resistor connected to the circulator also effectively terminates harmonic energy caused by the plasma non-linearities. Multiple plasma chamber electrodes and radio frequency power sources may be similarly controlled.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: September 17, 1996
    Assignee: LSI Logic Corporation
    Inventors: Roger Patrick, Frank A. Bose
  • Patent number: 5550087
    Abstract: A process for manufacturing substrate including a non-conductive support layer and a plurality "n" of conductive leads disposed on the support layer. The leads are arranged in a generally radial pattern about a central point on the support layer, each of the leads having a width "w" and spaced a distance "d" from one another at their innermost ends, thereby forming a generally square opening of side dimension "s". The substrate accommodates semiconductor dies ranging in size from smaller than the opening, to approximately equal to that of the opening, to substantially larger than the opening, such as four times the size (linear dimension) of the opening. The die is bonded to the substrate. Other elements of a semiconductor device assembly are added to the resulting structure.
    Type: Grant
    Filed: January 3, 1994
    Date of Patent: August 27, 1996
    Assignee: LSI Logic Corporation
    Inventor: Richard Brossart
  • Patent number: 5545923
    Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: August 13, 1996
    Assignee: LSI Logic Corporation
    Inventor: Ivor Barber