Abstract: During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.

Abstract: In a branch processing unit a branch history table is accessed by a branch instruction address associated with a scanned branch instruction before the entire address has been computed. The branch history table is partitioned into a first memory array associated with even instruction addresses and a second memory array associated with the odd instruction addresses.

Abstract: A method for selectively prefetching a cache line into a primary instruction cache within a processor from main memory allows for cold cache instruction prefetching of additional cache lines when the requested cache line does not reside within either the primary or secondary cache associated with the processor and there are not unresolved branches associated with the requested instruction in the cache line.

Abstract: Logic circuitry provides a fast resolution of conditional branch instructions in a high-performance superscalar processor. The logic circuitry facilities early (fast) resolution of a subset of conditional branches located within the first position of the primary instruction buffer within the processor enabling the overall branch processing logic to bypass history table-based prediction logic for such branches without crossing the cycle boundary. Thus, penalties associated with possible mispredictions for this subset of conditional branches are avoided.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A driver circuit including of one or more fingers, or parallel driver circuits, senses for an overshoot or an undershoot condition of the signal transmitted onto a transmission line coupled to the driver circuit and compensates for such an overshoot or an undershoot by temporarily turning off the offending transition portion of the driver circuit, or finger portion. This is accomplished by turning off the transistor applying one of the two supply voltages coupled to the output transmission line. Effectively, the compensation circuitry within the driver circuit more closely matches the output impedance of the driver circuit to the impedance on the driven transmission line.

Abstract: Circuitry within a system memory controller of a data processing system enables an M-bit processor to address a memory location that requires an N-bit address, wherein N is greater than M. Thus, a less than 48-bit processor will be able to access IPL code resident within a 48-bit memory system. An M-bit address is received from a processor and then extended into an N-bit address with a mask of N-M bits. The extended address is compared with an N-bit address representing the memory location to be addressed, and the extended address is then selected to access the memory location when the extended address equals the N-bit address representing the memory location.

Abstract: Within a microprocessor, multiple synchronous clock signals of arbitrary integer and non-integer ratios are produced with conventional digital divider circuitry. The various integer and non-integer clock signals can be provided to processor circuitry, bus circuitry, and coupled memory circuitry. Non-integer ratio clock signals can be produced out-of-phase with the system clock signal.

Abstract: A multiplier circuit within a CPU has its selections of partial products reordered in a unique manner so that shift left capabilities are eliminated and the hardware is required to only perform shift right operations. This allows for reduced circuit sizes in several components within the multiplier circuit in order to save area, speed computation time, and reduce power consumption on the chip.

Abstract: Circuitry within a processor delays the launching of data onto an external bus by a factor that is proportional to the ratio of an internal processor clock speed to the system or external bus clock speed. This delay provides a delay in the launching of data to external bus devices so that these slower speed external bus devices have enough time to capture the data.

Abstract: A matrix addressable flat panel display includes a flat cathode operable for emitting electrons to an anode when an electric field is produced across the surface of the flat cathode by two electrodes placed on each side of the flat cathode. The flat cathode may consist of a cermet or amorphic diamond or some other combination of a conducting material and an insulating material such as a low effective work function material. The electric field produced causes electrons to hop on the surface of the cathode at the conducting-insulating interfaces. An electric field produced between the anode and the cathode causes these electrons to bombard a phosphor layer on the anode.

Abstract: PowerPC external control instructions are utilized to pass a translated address to a transfer engine located in the system memory controller, together with previously transferred parameters into control registers within the memory controller. An accelerated data movement is accomplished between system memory and an input/output device with a minimum of processor overhead and bus bandwidth utilization. This method is useful for transferring large amounts of data between memory and such devices as graphics adapters or multimedia devices.

Abstract: The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.

Abstract: Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches. A directory field entry provides an indication of whether or not a particular cache line in the L1 cache is also included in the L2 cache.

Abstract: Control circuitry is used to select M entries from an N-entry storage array by viewing the array from both ends. Beginning at both ends of the array, particular bit values or entry content is looked for by the control logic. Once found at both ends, these entries are then used to produce control signals to be sent to a pair of muxes to remove these entries. Then a subset of the original array consisting of the remaining entries of the array is then iterated upon by a similar set of control circuitry for finding and removing the next M entries from the storage array.

Abstract: Logic circuitry implemented in a pipeline manner receives a request signal along with received data into the pipeline and proceeds to insure that each successive stage within the pipeline is placed into a standby state and out of a precharge state previous to the arrival of the data wave into each of the successive stages. The circuitry also resets each of the stages after a stage has evaluated the data. The logic circuitry may be employed within a multiplier array in a processor.

Abstract: A system and method to use stream filters to defer deallocation of a stream based on the activity level of the stream, thereby preventing a stream thrashing situation from occurring. The least recently used ("LRU") stream is deallocated only after a number of potential new streams are detected.

Abstract: A "no select state" is implemented with self-resetting CMOS logic circuitry so as to essentially disable the resetting function of this logic circuitry when the logic circuitry is in an idle state. As an example, within a multiplier circuit in a processor, the selection inputs to a multiplexor circuit are de-selected when there is no need for the multiplier circuitry.

Abstract: A self-timed control circuit for self-resetting CMOS logic circuitry provides handshaking between macros to ensure that all data inputted to a particular macro is maintained by the source macros until all data inputs have been received. A data output signal from a macro is maintained until the macro receives a complete signal from all receiving macros indicating that the receiving macros have received all data inputs supplied to them.

Abstract: A field emission cathode for use in flat panel displays is disclosed comprising a layer of conductive material and a layer of amorphic diamond film, functioning as a low effective work-function material, deposited over the conductive material to form emission sites. The emission sites each contain at least two sub-regions having differing electron affinities. Use of the cathode to form a computer screen is also disclosed along with the use of the cathode to form a fluorescent light source.