Abstract: In digital systems clock signals are generated from an external clock reference signal for the purpose of synchronization with the aid of a phase-control loop 1 incorporating a frequency-controllable oscillator 2. In practice synchronization problems occur due to the phase inaccuracy of these clock signals relative to the clock reference.By a two-level control of the oscillator frequency in a plurality of cycles, located within a period of the clock reference signal, using a pulse-width modulator 12, the phase accuracy of a clock signal to be derived from the oscillator output signal is improved.In a preferred embodiment the loop 1 comprises: storage means 16, control means 17 and selection means 18 for providing in accordance with a given phase control strategy a phase-accurate oscillator output signal, this accuracy already being obtained on a small time scale.

Abstract: Higher order digital transmission system including a multiplexer having N parallel inputs to which tributary input signal streams are applied, and a demultiplexer having N parallel outputs from which the tributary signal streams are taken. The signal processing operations, such as scrambling, justifying, line coding, error monitoring and word synchronization are effected before the multiplexer and after the demultiplexer, consequently not at the full line rate.

Abstract: In a d.c. voltage converter 1 including a series arrangement of a transformer 3 and a pulse-switched current source 7 the power converted by means of the transformer 3 is kept constant with the aid of a control circuit 13. In the event of a short-circuit in one of the secondary windings 5-1, 5-2 a voltage drop across an auxiliary winding 6 of the transformer 3 is used to limit the converted power during the short-circuit.

Abstract: Integrated circuit chips included on a wafer typically include multiple internal test pads. During diagnostic testing of the wafer, a fine-point test probe is utilized to contact the pads. As feature sizes decrease, the task of consistently and reliably probing very-small-area internal test pads becomes increasingly difficult and time-consuming. In accordance with a feature of the present invention, each internal test pad on a chip is designed to include an interior opening. This provides a continuous interior edge which reliably limits sliding of an inserted tip while ensuring good electrical contact between the tip and the pad being probed.

Abstract: An arrangement for compensating for non-linear distortion in an input signal to be digitized, comprising an analogue-to-digital converter (2) for converting the input signal into an amplitude-time discrete output signal, means (3) for deriving a set of coefficients which are associated with an orthogonal signal representation of a signal related to the input signal, a memory (4) in which a Table with correction values is stored, means for addressing the memory for reading a correction value from the Table, each of the coefficients determining an address for the memory, means (5) for adding together the correction value and the analogue-to-digital converter output signal for providing a linearized signal, and an adaptive control loop (7,8,16,18) for substituting in the Table the new correction value for the correction value read.

Abstract: An elongated source of charged particles is utilized in a lithographic system to form multiple focused electron (or ion) beams arranged in a linear array. The basis for an extremely high-throughput lithographic system especially suited for direct writing applications is thereby provided.

Abstract: A glass reflow step to round off sharp edges of contact vias is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither changes in the composition of the glass nor modifications in the processing parameters of reflow were effective to avoid the overhang phenomenon. In accordance with the invention, it has been discovered that the overhang problem can be consistently avoided if the ratio of glass thickness to via-to-via spacing is about .ltoreq.0.393.

Abstract: A chuck for holding a workpiece (e.g., a semiconductor wafer) in a vacuum comprises a curved reference surface. By clamping the edges of the workpiece and maintaining its backside against the curved surface (or against pins mounted on the surface), the frontside of the workpiece can be thereby established in a precise equidistant relationship with respect to the reference surface. Such a chuck is advantageous for holding wafers to be lithographically patterned in a high-resolution way by electron-beam, ion-beam and X-ray-beam techniques.

Abstract: In wafer-scale-integrated assemblies, microminiature transmission lines are utilized as interconnects on the wafer. The extremely small cross-sectional area of a typical such line results in its total line resistance being relatively large. Such a line exhibits signal reflections and resonances. In practice, it is not feasible to eliminate these effects by conventional load termination techniques. As a result, the frequency at which digital signals can be transmitted over such a line is typically limited to well below its so-called resonance limit. In accordance with a feature of the invention, the structural parameters of each line are selected to meet specified design criteria that ensure optimal high-frequency performance of the line.

Abstract: A deep-UV step-and-repeat photolithography system includes a narrow-bandwidth pulsed excimer laser illumination source and an all-fused-silica lens assembly. The system is capable of line definition at the 0.5-micrometer level. One significant feature of the system is its ability to perform wafer focus tracking by simply changing the frequency of the laser.

Abstract: A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a modified version of the doping technique described in U.S. Pat. No. 4,471,524 and 4,472,212. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.

Abstract: Selective electroless plating of cobalt or nickel is utilized to form conductive plugs in high-aspect-ratio vias in VLSI devices. Particularly good results are obtained when an active or catalytic film is formed on the via bottoms to serve as a plating base.

Abstract: The standard silicon wafer of a conventional wafer-scale-integrated assembly is doped to render it highly conductive. Additionally, a conductive layer is formed on the bottom of the wafer. The bottom-side layer forms an easily accessible ground plane of the assembly. Moreover, this layer and the conductive silicon constitute one plate of an advantageous wafer-size decoupling capacitor. A nearly continuous power layer and a relatively thick layer of silicon dioxide on the top side of the assembly form the other elements of the decoupling capacitor. Additionally, the nearly continuous power layer constitutes an effective a-c ground plane for overlying signal lines.

Abstract: Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, donor doping is carried out in a two-step procedure. In each case, current injection into the channel is enhanced and leakage to the substrate is reduced while still maintaining substantial immunity to parasitic bipolar transistor action (MOS devices) and to latchup (CMOS devices).

Abstract: It is known to utilize dielectric-filled trenches in a CMOS integrated-circuit device to achieve electrical isolation between adjacent n-channel and p-channel regions. In that way, latchup-free operation of the device is ensured. But inversion effects along the walls of the trenches can cause high leakage currents, undesirably high parasitic capacitances and even shorting together of source/drain regions. In accordance with the invention, a nonlithographic technique including selective anodic oxidation is employed to selectively mask the sidewalls of the trenches. Each sidewall can then be independently doped thereby effectively eliminating the possibility of inversion occurring therealong.

Abstract: Selective wet or plasma anodization is utilized for forming a relatively thick dielectric layer only at the bottoms of trenches included in DRAM and/or CMOS devices. In that way, the electrical characteristics of trenches that include bottoms having surface roughness and/or sharp or irregular corners are significantly improved. Additionally, electrically isolated capacitor structures in elongated trenches formed in DRAM devices are thereby made feasible.

Abstract: One or two linear arrays of photodetectors are combined with optical elements to form an arrangement capable of determining the X-Y location of a focused laser beam or other light spot. The resulting arrangement is characterized by low cost and by excellent resolution, stability and linearity. Moreover, the arrangement provides output data that can be easily and quickly processed. The combination is adapted, for example, for use with zone plates in aligning masks and wafers in semiconductor fabrication.

Abstract: A high-precision alignment pattern for fine-line device fabrication comprises unique marks. The pattern is utilized to align a mask or reticle with respect to a wafer and/or to evaluate actual level-to-level registration achieved between a set of masks or reticles and a wafer. One mark of the pattern comprises two spaced-apart parallel lines. The other mark comprises a notch or arrow-head including an apex portion. In practice, the orientation between the apex portion and the associated parallel lines of the pattern can be read relatively easily with high accuracy.

Abstract: An improved X-ray source for a lithographic system comprises a double-angle conical target. The target is characterized by a small apparent source diameter and an efficient cooling system. Submicron resolution and high-power operation are thereby made feasible.

Abstract: One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.