Abstract: Mask-to-wafer alignment in X-ray lithography is advantageously carried out utilizing zone plate marks formed on the mask and wafer. In practice, it has been observed that the intensity and in some cases even the location of the centroid of the light spot formed by a zone plate mask can vary during alignment as the mask-to-wafer spacing is changed.The present invention is based on the discovery and analysis of the causes of such variations. Based thereon, applicants have devised a modified mask structure which, when used with a wafer in a zone plate alignment system, enables mask-to-wafer alignment to be made more easily and more reliably than was possible heretofore. The modified mask structure includes a localized blocking layer over each zone plate on the mask. This layer allows only a negligible portion of the light employed to illuminate the zone plates on the mask to propagate into the mask-to-wafer space.

Abstract: One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Abstract: An electron emission system includes a high-brightness field-emitter cathode. Advantageously, the tip of the cathode is shaped to minimize structural variations caused by surface tension forces. In addition, an electrode assembly associated with the cathode is designed to establish electric field forces that are opposite and at least approximately equal to the surface tension forces acting on the tip. The electric field forces can be adjusted to establish a highly stable operating condition without altering the value of electron beam energy for which the overall system was designed. Moreover, the current density of the beam at a writing surface can be selectively varied without changing prescribed operating parameters of the cathode. The resulting system is characterized by excellent emission stability, low noise and a useful operating life of at least several thousand hours.

Abstract: A package for a semiconductor chip includes as an integral part thereof a frame-shaped multilayer ceramic capacitor. The chip is mounted within the capacitor structure. Conductive portions of the capacitor serve as the terminals and plates of the capacitor and as planar power and ground members for interconnecting an external power supply to the chip. By means of these planar members, power is distributed to the chip in a low-impedance, substantially transient-free manner without utilizing any of the multiple signal leds emanating from the package. Moreover, the signal leads are separated from the ground plane by a low-dielectric-constant material. As a result, the signal leads are minimally loaded and are characterized by a relatively constant impedance selected to optimize signal transfer to and from the chip.

Abstract: For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured.The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.

Abstract: To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.

Abstract: A single stage high performance operational transconductance amplifier consists of a pair of p-channel load field effect transistors, a pair of n-channel type cascode field effect transistors, a pair of n-channel differential field effect transistors and an n-channel current source field effect transistor. This amplifier has improved performance in terms of noise and power supply rejection as compared to conventional CMOS amplifiers.

Abstract: Compact apparatus characterized by cleanliness of operation, high throughput and low cost is designed for automatically loading and unloading wafer-carrying trays that are designed to be mounted in the reaction chamber of a processing system. A key component of the apparatus comprises a unique wafer vacuum chuck.

Abstract: Annealing a titanium-rich carbide film deposited on silicon produces, in a single processing step, both a stable titanium silicide contact and a titanium carbide diffusion barrier between the silicide and a subsequently formed overlying layer of aluminum. Reliable low-resistance contacts to VLSI devices are thereby provided in a cost-effective fabrication sequence.Other metallization systems, comprising a silicide and a diffusion barrier to aluminum formed in a single processing step, are also described.

Abstract: In a feedback-type buffer amplifier designed to be interposed between a reference voltage source and a capacitive load, the output of the amplifier is applied to each of two precisely matched or scaled source follower circuits. The voltages appearing at respective output nodes of the source follower circuits are designed to be identical to each other. But, significantly, the nodes are decoupled from each other. One output node is included in the feedback path of the buffer amplifier, whereas the other node constitutes the output terminal of the composite arrangement. Perturbations or phase shifts due to the load are thus effectively decoupled from the feedback path of the amplifier. A fast-settling stable overall configuration is thereby provided.

Abstract: In a high-speed digital data system, it is advantageous to sample incoming data pulses at the baud-rate rather than at the Nyquist-rate. In such a system of the type that includes a dispersive channel (e.g., an unloaded subscriber twisted pair with bridged taps), effective baud-rate sampling and reliable pulse recovery at a receiver depend on the availability of a suitable pulse synchronization or timing recovery technique. In accordance with this invention, timing recovery is based on the recognition that the precursor portion of the response of the channel is relatively invariant and predictable. By selecting a specified threshold point in a small-amplitude region of the precursor portion, a basis is provided for generating accurated bipolar error signals that insure consistent baud-rate sampling of received pulses.

Abstract: Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, donor doping is carried out in a two-step procedure. In each case, current injection into the channel is enhanced and leakage to the substrate is reduced while still maintaining substantial immunity to parasitic bipolar transistor action (MOS devices) and to latchup (CMOS devices).

Abstract: Many signal processing applications of practical importance (for example, continuous-signal filtering) require high-precision temperature-insensitive transconductance elements. In accordance with one feature of this invention, a reference transconductance element is included in a control loop. The element consists of a MOSFET device or a MOSFET circuit in the loop. In the loop, the transconductance of the reference element is determined solely by the value and switching period of a switched-capacitor. The transconductance of the element is in effect thereby precisely matched against the conductance of the switched-capacitor.As the temperature of the chip varies, a control voltage is generated in the loop to maintain the transconductance of the reference element constant. This same control voltage is applied to other similar elements included in circuits (for example, filters) on the chip. In that way, the transconductances of these other elements are also matched to that of the switched-capacitor.

Abstract: A polyarylate polymer is deposited on a substrate in accordance with a fabrication procedure that ensures an adherent low-stress conformal coating. Such a coating is advantageous for use in a number of industrial applications of practical importance.

Abstract: At least three spring-mounted members disposed around the periphery of an aperture in a wafer-mounting plate are arranged to engage and securely hold edge portions of a semiconductor wafer to be processed. When the spring-mounted members are actuated toward the front side of the plate, a wafer can be freely moved into or out of the aperture from the back side of the plate by means of a vacuum chuck that contacts only the back side of the wafer. After a wafer to be held is inserted within the aperture, the actuated members are released. The released members move toward the back side of the plate and thereby engage the edges of the inserted wafer and exert radial holding forces thereon. The back side of a wafer so mounted is adapted to be brought into resilient engagement with a pedestal element in a processing chamber, thereby ensuring good thermal and electrical contact between the wafer and the pedestal element.

Abstract: An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature. Owing to a high segregation coefficient of arsenic in silicon dioxide, nearly all of the arsenic in the source layer is driven into extremely shallow source and drain regions which acquire high surface concentrations.

Abstract: A method for forming a shallow and highly concentrated arsenic doped surface layer in a silicon bulk region includes the steps of forming an arsenic doped polysilicon layer in contact with a preselected area of a bulk region surface in which the surface layer is to be formed and completely oxidizing the polysilicon layer at a rate exceeding the rate at which arsenic diffuses in the bulk region. Since arsenic has a relatively high silicon/silicon dioxide segregation coefficient and the oxidation rate exceeds the arsenic diffusion rate, arsenic accumulates at the silicon dioxide/silicon interface during oxidation, and nearly all of the arsenic in the region of the polysilicon layer above the preselected area is driven into the bulk region surface by the oxidation to form an impurity layer having a very high surface concentration of arsenic.

Abstract: A unique socket assembly is designed to interconnect a flat-pack-packaged integrated-circuit chip to a printed-circuit board in a manner that permits easy insertion and withdrawal of the packaged chip from the assembly. A base portion of the assembly includes a recess into which conductive cantilevered elements extend. When the packaged chip is positioned on these elements within the recess and a lid is placed on the base, secure but not permanent electrical contact is established between the elements and contact regions on the chip package.

Abstract: The compounds TiSi.sub.2 and TaSi.sub.2 have been found to be suitable substitutes for polysilicon layers in semiconductor integrated circuits. Suitable conducting properties of the compounds are ensured by providing a relatively thin substrate of polysilicon.

Abstract: In certain negative resists utilized for high-resolution lithography, cross-linking persists even after the exposing radiation is removed. This phenomenon causes exposed features to become enlarged. In accordance with the present invention, cross-linking in exposed resist regions is effectively quenched by purposely subjecting the exposed regions to oxygen immediately following exposure to cross-linking radiation. In, for example, full-field or step-and-repeat X-ray lithography, such quenching enables the consistent attainment of submicron features.