Abstract: A method and apparatus for locally delivering an active agent to a selected site in a body lumen using a liquid core laser catheter having a flexible tube for insertion into the lumen, a conduit housed within the tube for coupling a flow of light transmissive liquid from an external source to the site, and an optical fiber housed within the tube for coupling laser energy from an external source to the site. In one embodiment, the conduit has a sidewall capable of internally reflecting light into the liquid in the conduit so that the liquid waveguides the laser energy through the conduit to the site.

Abstract: There is provided a mute control circuit which is simplified to efficiently remove switching noise during the muting of each output and reducing the number of connection pins required for a given integrated circuit. The mute control circuit includes a pulse generator for receiving the each mute signal and generating a control pulse; a charge/discharge signal generator for receiving the control pulse and generating a charge/discharge signal and a switching control signal; a controller for receiving the charge/discharge signal and controlling the mute operation of the output terminal according to the switching control signal; and a switching signal generator for receiving the mute signal, generating a switching signal according to the switching control signal of the charge/discharge signal generator, and supplying the switching signal to the controller.

Abstract: Disclosed is an instruction-level method and system for prefetching data or instructions of variable size to specified cache sets. A prefetch instruction containing binary fields allows the compiler, loader or runtime software to control cache prefetching and reduce thrashing by providing the prefetch hardware with information as to the optimal cache set location and the optimal amount of data to be prefetched. Support of Harvard architectures with separate instruction and data caches is provided by separate software control of instruction and data caches. The cache set number is identified to indicate into which set the information is to be preloaded. The size field provides a variable prefetch size. An address field indicates the address where prefetching begins.

Abstract: A semiconductor memory device having a unit memory cell consisting of, a ferroelectric capacitor having a first and second electrodes, and an access transistor connected to the first electrode of the capacitor and to the bit line, is disclosed. An imprint compensation circuit for applying a predetermined voltage to the first electrode through the write path of the memory device, or for applying a signal in the form of pulse to the second electrode, where data access of the memory device is prohibited, in order to imprint the ferroelectric capacitor in first and second directions from the reference point, creating a normal polarization characteristic.

Abstract: Disclosed is a system and method which systematically diagnoses emissions test failure by applying the rules of a knowledge base to predict the cause of vehicle emissions failures. Classifiers are used to form predictions. The classifier is the data structure used in the automobile emission testing inspection lane by the lane diagnostic subsystem to provide a diagnosis for a particular vehicle. Its output is the likelihood that a vehicle suffers from a given failure based on the values of characteristics such as its emissions test results and the vehicle's description. The classifier predictions are then used to prepare a failure report that is given to the motorist for use by his or her repair technician. In another feature of this invention, the classifiers are continuously updated in a learning process based on new repair records. The learning processes periodically analyzes the data and updates the knowledge base to include new or revised classifiers.

Abstract: A simulation based power analysis tool extracts "expected" current waveforms from simulation results. These expected waveforms are then used to represent the power consumption for a corresponding circuit cell or groups of cells from which the waveform is derived. The expected waveform is a statistical representation of a current derived over a number of cycles. The expected waveform is derived by recording the starting time of each power arc with respect to a tool defined clock period. The width of the waveform is derived from the average current, propagation delay and intrinsic delay for arc. The expected waveform can take several forms depending on the accuracy required. Each form has a corresponding memory storage requirement. The starting time for each arc can be stored, which yields the most accurate "true" expected waveform. Alternatively, the minimum, maximum and average starting times for a given power arc can be stored from which a "weighted min-max" expected waveform can be constructed.

Abstract: A method and apparatus for implementing a prefetch scheme in which a plurality of data are simultaneously read from memory cells of sequential addresses synchronized to an external signal and serially transferred from the memory cells to a temporary latch circuit which has a number of bits corresponding to the member of bits in the prefetch scheme. The bits in the temporary latch circuit are multiplexed and sequentially driven out of the memory device. The memory device includes a plurality of memory cells which are connected to an input/output line pair through a plurality of column select gates, each of which is controlled by an independent chip select line. A sense amplifier is connected to the input/output line pair for sensing and amplifying data from the input/output lines and to transmit data to the input/output lines. A data output buffer transfers the data from the sense amplifier to the outside of chip.

Abstract: A light expanding system for converting a light beam generated from a point-like light source into a collimated linear or planar light beam is disclosed herein. According to an embodiment of the invention, a system for producing a linear light beam includes a beam collector and a light pipe adjacent to which a multiplicity of specially configured microprisms are located. The light expanding system according to this embodiment is suitable for use in devices utilizing a linear light beam, such as a scanner. According to another embodiment of the invention, a system for producing a planar light beam includes, in addition to the beam collector and light pipe described above, an additional light pipe with adjacent microprisms. The light expanding system according to this embodiment of the invention can be used, for example, in displays, road signs, medical research equipment, instrument meters or jewelry; to light pictures or art work; or as part of a see-through lighting system far use in dentistry and surgery.

Abstract: An output control circuit for a semiconductor memory device allows the output data to be controlled by a write enable line and/or an output enable line in hyper page mode. An output write enable control signal is generated in response to a column address strobe signal, an output enable signal and a write enable signal. A precharge signal is generated in response to the output write enable control signal, thereby allowing a data bus line to be precharged in hyper page mode. The output enable signal and the write enable signal can be selectively coupled to an output write enable control signal generating circuit to allow the output control circuit to operate in different modes. A trigger signal, which controls a data output buffer and driver circuit, is controlled in response to a latch signal. The latch signal is generated by latching the write enable signal in response to the column address strobe signal.

Abstract: Methods and apparatus for controlling output buffer circuitry in a synchronous semiconductor memory device. An internal clock signal is generated and logic provided to provide a control signal that enables that output buffer circuitry for a read operation. An internal clock signal is generated synchronized to the external or system clock signal. An intermediate control signal is triggered by the internal clock signal at a selected number of cycles less than the memory latency period after a read command, and then the control signal for enabling the output buffer is asserted on a subsequent cycle of the internal clock signal, thereby ensuring at least a predetermined minimum time for the output buffer control signal to propagate through the memory device before data is transferred out of the device.

Abstract: The capture range and stability of a phase locked loop are improved by adjusting the free running frequency of a voltage controlled oscillator in response to the output signal of the phase locked loop. The output signal is filtered and amplified, and then compared to a reference signal from the voltage controlled oscillator which is indicative of the free running frequency. A direct current level capture circuit compares the filtered and amplified output signal with the reference signal and generates a control signal which adjusts the free running frequency so as to equalize the output signal and the reference signal. The control signal is generated by sequentially and consecutively enabling a series of filter reset circuits. A switch control circuit controls two feedback paths between the phase detector and the voltage controlled oscillator. The first feedback path includes a low pass filter and is selected by the switch circuit for normal operation.

Abstract: Several short segments of an otherwise continuous sound are recorded and stored in a digital memory. The stored segments are concatenated together to form a sound sequence of arbitrary length, based on selecting the next sound segment according to some statistical algorithm. The selected algorithm may be simply a random or pseudo-random selection, or it may provide a probability weighting to emphasize some sound records over others, or some combination of factors also affected by external stimuli such as light, heat or operator input. Apparatus for generating random sequenced digital sound are disclosed. Another aspect of the invention is logical sequence sound in which the selection of sound segments proceeds according to a logical sequence which is programmable.

Abstract: A redundancy decoding circuit for a semiconductor memory device is shown which includes a comparator which decodes and outputs a redundant memory cell address in response to an address signal, where the comparator includes internal fuses that are coupled to an output terminal of the comparator and which can be selectively cut in order to determine the redundant memory cell address. The redundancy decoding circuit also includes a driving unit which supplies a driving current to the output terminal of the comparator in response to a switching control signal. A pulse generator generates a power up pulse having a predetermined width responsive to power up of the redundancy decoding circuit. A switching control signal generator, which includes a master fuse connected in series with a switching element, generates the switching control signal at a predetermined voltage level in response to the power up pulse generated by the pulse generator even when the master fuse is incompletely cut.

Abstract: A switch-control integrated circuit for a switch-mode power supply (SMPS) capable of consistently limiting the peak current value of an output supply voltage irrespective of a temperature change. The circuit includes a switching transistor of the SMPS and a sensing resistor coupled to a drain of the switching transistor for sensing a drain current of the switching transistor to produce a peak current value detection voltage. A voltage generating circuit generates a feedback voltage which varies depending on the temperature condition equal to that of the sensing resistor. A comparator compares the temperature dependent voltage, received at a first input, with the temperature dependent peak current value detection voltage, received at a second input, to produce a temperature independent control signal. A protection circuit, coupled between the comparator and the switching transistor, interrupts the control signal if an abnormal operation of the voltage generating section is detected.

Abstract: A mixer includes a doubly-balanced mixer core, an RF input section coupled to the mixer core, and a biasing circuit coupled to the RF input section. The RF input section includes a first transistor coupled to a first input of the mixer core for supplying a first current thereto. The base of the first transistor is driven by an RF input current, as a result, the first current is responsive to the RF input current. The RF input section also includes a current mirror coupled to the first transistor, which mirrors the sum of the first current and the RF input current to produce a second current that is complementary to the first current for small variations of the RF input current. The current mirror is coupled to a second input of the mixer core to supply the second current thereto. A biasing circuit is coupled to the RF input section to establish a quiescent value of the first current. Padding resistor can also be used in the RF input section to provide a predetermined input impedance to the RF input current.

Abstract: An internal column address generation circuit generates an internal column address by utilizing an asynchronous counter. The circuit includes a column address buffer for synchronizing an initially received external address with an external system clock to generate the internal column address, and for synchronizing a counting bit output signal received at an internal input node with the external system clock to generate the internal column address; and an asynchronous counter connected to an output node of the column address buffer, for generating the bit output signal having the same or opposite phase as/to a phase of the internal column address received from the column address buffer, in response to a carry generation state.

Abstract: A control circuit controls a battery charger so as to prevent damage to NiCAD or NiMH batteries resulting from overheating due to overcharging. During charging, the battery voltage is monitored through a filter, buffer, amplifier and sample and hold circuit. The sampled voltage is time differentiated to determine its rate of change, and a control signal is generated for switching the battery charger from a rapid charge mode to a trickle charge mode when the negative rate of change of the battery voltage exceeds a pretermined reference voltage, thereby identifying that the battery voltage has started to decay from its peak voltage.

Abstract: A frame corner joining apparatus for joining two metal picture frame members at a predetermined angle to form a frame corner. The joining apparatus includes first and second legs disposed at the predetermined angle relative to each other, each leg receivable in a corresponding frame member channel. Each leg includes a fillet surface and a sloping surface, having a slot and a wedge piece with tab received in the slot. The wedge piece may be in two positions: an unlocked position in which the wedge piece is at the lowest point on the sloping surface, and a locked or raise position in which the top side of the wedge piece engages a surface of the picture frame. The wedge piece may be adjusted manually with needle nose pliers or automatically with a pneumatic device until the fillet surface of the frame corner joining apparatus tightly abuts the back lip edge of the picture frame member.