Abstract: A method of controlling the buffering of output data by synchronizing with an external system clock, including the steps of generating an internal clock pulse, transferring data from a chip to a pair of data output lines in response to the internal clock pulse, generating an output mode control signal in synchronism with the internal clock pulse, gating the output mode control signal from the first edge of the internal clock pulse to the first edge of the next internal clock pulse to produce an output control signal, and driving data output to an output pad in response to the output control signal is disclosed.

Abstract: A concrete dowel slab joint system is provided for maintaining adjacent sections of concrete in alignment during contraction and expansion of the concrete, and for transferring shear stresses and bending moments across a joint formed between adjacent concrete slabs. It includes a sleeve assembly for receiving and maintaining the dowel bar therewithin. In this is way, the dowel bar does not transmit substantial shear stresses to the concrete during the contraction and expansion of the concrete. The sleeve assembly comprises an elongate sleeve body having an outer surface and an inner surface, and defines a hollow interior compartment, (b) at least one closed end, and (c) a sleeve member. Preferably, at least one collapsible spacer member is located within the hollow interior compartment. The spacer member is collapsible by interactive forces exerted by the dowel bar moving in a lateral and/or longitudinal path within the hollow interior compartment in response to the expansion and contraction of the concrete.

Abstract: A sense amplifier has a pair of output terminals and a first pair of pull-up transistors. A second pair of transistors is connected between the output terminals and a pull-down node. The gate electrodes of the second pair are cross-coupled to the output terminals. A third pair of transistors is connected between the output terminals and the pull-down node and have gate electrodes coupled to input potentials. A fourth pair of transistors is connected between the output terminals and the pull-down node and also have gate electrodes coupled to input potentials.

Abstract: Disclosed is a method and system for providing for the prefetching of data or instructions. A prefetch instruction which is in an instruction stream is processed by memory management unit (MMU) where prefetch cache control information is placed as part of the already existing prefetch instruction. Once processed by the MMU, the prefetch instruction thus contains binary fields allowing the operating system or runtime software to control cache prefetching by assigning values to the binary fields which provide the optimal cache set location and the optimal amount of data to be prefetched and thus reduces thrashing.

Abstract: A data output buffer circuit for a semiconductor memory device operates with two separate power supplies and prevents malfunctions caused by the sequence in which the power supplies are energized. At lease one discharge transistor is used to remove charge from the gate of one or more NMOS push-pull transistors in an output buffer which can be floating in a charged state if one of the power supplies is energized before the other. In one embodiment, the gates of two discharge transistors are cross-coupled to the gates of the push-pull transistors to assure that at least one of the push-pull transistors are turned off. In an alternative embodiment, one or more discharge transistors are connected to the gates of at least one push-pull transistor and are controlled by a pulse generator that generates a pulse signal in response to variations in the voltage of the power supply for the push-pull transistors.

Abstract: A digital data level control circuit adopting a digital-to-analog conversion control mode is provided, in which a capacitor for removing popcorn (POP) noise is used towards an output end of a digital-to-analog converter portion and switching of a controller is controlled by a microcomputer to perform a desired level control, thereby effectively removing the POP noise. The digital data level control circuit includes a digital-to-analog converter portion for converting the digital data into analog data, a controller connected to an output end of the digital-to-analog converter portion, for controlling the level of the analog-converted data, and an out level control portion connected to one end of the controller, for smoothly controlling the level of the analog-converted output from the digital-to-analog converter portion.

Abstract: A multiarch assembly comprises first and second parallel archwires, each formed into a segment of an orthodontic archform spanning a plurality of a patient's teeth, a multiarch bracket having a bracket body defining reentrant archwire slots along opposite occluso-gingival sides of the base for receiving and seating the first and second archwires in a base portion therein, the base portions of the slots having a predetermined center-to-center occluso-gingival spacing; and an interarch connector having a connector body formed of a resilient material with first and second archwire openings spaced apart along an occluso-gingival axis of elongation and sized for the first and second archwires to be threaded therethrough, the connector body being resiliently deformable along the axis of elongation to enable the archwires to be spread apart and then to urge the archwires toward one another in a direction of contraction along the axis of elongation; the holes in the interarch connector being spaced center-to-center a

Abstract: A method for generating a pulse width modulated signal having a linear relationship to a digital input data signal includes generating a series of PWM component signals, multiplying (ANDing) each of the component signals with one bit of the digital input data, and then summing (ORing) the resulting signals to generate the PWM signal. Each of the component signals corresponds to a single bit of a multi-bit, monotonically increasing counter signal. Each component signal is generated by asserting the component signal only when the corresponding counter bit is asserted and the lower ranking counter bits are not asserted. Two's complement input data can be accommodated by selectively inverting the lower ranking digital input data bits in response to the logic state of the highest ranking input data bit which acts as a sign bit. The multi-bit counter signal is generated by a counter which increments the counter signal by one for each cycle of a clock signal.

Abstract: A drill bit assembly includes a driver adapted for attachment to a down hole pneumatic hammer. A pilot bit is coupled to the driver in a manner permitting rotational and axial movement between driver and pilot bit. A series of underreamer arms are disposed intermediate the driver and the pilot bit and engage a centrally disposed cam block on the pilot bit. Pivot pins of the underreamer arms are journaled in and move with the driver during partial rotation of the driver during arm deployment and retraction. Passageways in the driver and pilot bit direct compressed air to the working surface of the bit for discharging particles upwardly through channels in the bit and driver. Inclined surfaces on the underreaming arms cooperate with the lower end of a casing to contribute to arm retraction prior to removal of the assembly through the casing.

Abstract: A sense amplifier for transferring data between a data input/output line and a bit line in a nonvolatile semiconductor memory device includes two isolated current paths to prevent data collisions. A transistor transfers a bit of input data from the data input/output line to a first terminal of a two-terminal latch in response to a load control signal. The second terminal of the latch is connected to the bit line. A second transistor transfers a bit of output data from the second terminal of the latch to the data input/output line in response to a read control signal. While the bit of input data is being transferred, the second transistor isolates the second terminal of the latch from the data input/output line.

Abstract: A dimmer rack utilizes removable connector modules for interfacing the rack to various types of standard electrical connectors in pre-existing lighting systems. The dinner rack includes a front bay for receiving dimmer modules, a rear bay for receiving the connector modules, and a patch panel for routing electrical power from the dimmer modules to the connector modules. Each connector module includes a rear panel having a connector for connecting the module to the patch panel and a front panel having a standard electrical connector for connecting the module to a lighting system. The connector modules can be fabricated with various types of standard electrical connectors.

Abstract: The present invention comprises a cascode circuit of the type having a first and second FET in a first leg and a third and fourth FET in a second leg comprising. The first and third FETs are switched between an on state and an off state substantially in tandem in response to a level change in an input signal to the cascode circuit. The second and fourth FETs are switched between an on state and an off state substantially in tandem in response to a level change in the input signal and substantially complimentary to the switching of said first and third FETS. A biasing signal is applied to a control electrode of the first FET responsive to transition of the input signal from a first level to a second level. A biasing signal is also applied to a control electrode of the third FET responsive to transition of the input signal from the second level to the first level.

Abstract: A data output buffer of a semiconductor memory device having a data output driver comprised of a pull-up transistor and a pull-down transistor includes a precharging circuit for precharging a gate terminal of the pull-up transistor of the data output driver to a power supply voltage level. Precharging the output driver reduces the load on the pumping voltage generator. This feature, together with precharging the pumping voltage generator itself, allow clocking the pumping voltage generator at a reduced clock rate to reduce power consumption without compromising operating speed of the memory device.

Abstract: A pulse-shaping circuit comprises a current limiter, which is connected in parallel with a voltage divider, for limiting a source voltage and enabling first and second voltage signals divided by the voltage divider to be constantly maintained, and an output voltage limiter which is provided to prevent a collector voltage of an output switching transistor from being increased to more than 0.1 V, so that an output pulse signal from an output terminal thereof may be lowered nearly to about 0.1 V when a low input pulse signal is applied to an input terminal thereof.

Abstract: A reference voltage generating circuit has a divider circuit for decreasing a received external power-supply voltage and for providing the decreased voltage at a reference voltage output terminal. A PMOS transistor clamps the reference voltage at a predetermined voltage level, one end thereof being coupled to the reference voltage output terminal and the other end being coupled to a ground. A compensating unit adjusts the substrate voltage of the PMOS transistor to compensate for level variations of the reference voltage in response to the level variations. Thus, variations in the reference voltage caused by changes in processing variables are compensated, thereby maintaining the reference voltage at a predetermined level.

Abstract: A standby current detecting circuit for use in a semiconductor memory device and method thereof are described. The memory device has a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines. A plurality of switches are associated with each memory cell. A current path supplies current to each memory cell through the switch associated with each memory cell. A plurality of decoders are provided with each decoder for detecting a standby current supplied on one such current path for the memory cell. Each decoder includes control logic for selectively opening and isolating the switch associated with the memory cell in a standby current detection mode.

Abstract: A close contact type image sensor having an improved structure and manufacturing process utilizes a body having integral reflective surfaces to eliminate assembly steps. The body and reflective surfaces are formed using different plastic materials in a single injection molding process. A material having highly reflective characteristics is used for the reflective surfaces. A light source is aligned with the reflective surface by pins in the sensor body which are inserted into holes in the light source. Alternatively, the light source can be mounted on a printed circuit board which has holes that are aligned with the pins. A self focusing lens is mounted in the body to focus reflected light onto a light detector which is mounted on a printed circuit board. A transparent cover piece is mounted in an opening in the body. Flat spring clips secure the printed circuit board to the body of the sensor.

Abstract: A semiconductor memory device comprising a memory cell array including at least two banks and a desired number of voltage pumping circuits each for pumping an input voltage to a desired level. The voltage pumping circuits are driven in response to at least two bank selection control signals. The voltage pumping circuits are arranged in the semiconductor memory device in a proper manner to efficiently perform the voltage pumping operation, so as to increase the pumping efficiency. Further, the proper arrangement of the voltage pumping circuits contributes to the integration of the semiconductor memory device.

Abstract: A semiconductor memory device achieves high speed operation while operating at a low power supply voltage by boosting the voltage level at the plate node of a memory cell during an access operation. The memory device includes a plate voltage generator which generates a variable voltage level. The plate voltage generator includes a pair of switches for coupling the plate node to either a conventional (1/2)VCC voltage generator or a power supply node in response to a control signal. The plate voltage generator also includes a pulse generator that generates a pulse signal for controlling the switches in response to the control signal. During a precharge period, the bitline pair is charged to VCC. The plate voltage generator charges the plate node to (1/2)VCC during the precharge state and then to VCC during an access operation. This boosts the voltage level at the storage node of the memory cell, thereby decreasing the time required to amplify the signals on the bitlines.