Abstract: A resonant convertor control system regulates a resonant AC current based on the amount of input power consumed by the system. The switching frequency and resonant AC current are limited by a phase difference assurance circuit that compares the phase of a drive signal with the phase of the resonant AC current. By detecting the phase of the resonant current instead of the resonant voltage, it eliminates the need for the costly components required to detect the resonant voltage. The system includes a main power supply for supplying a DC power signal and an inverter that converts the DC power signal to a resonating AC current signal responsive to a drive signal from a drive stage. An input current controller receives a first sense signal that indicates the power consumed by the main power supply and generates a first control signal that regulates the power consumed by the load.

Abstract: An initialization circuit for a semiconductor memory device includes an initialization signal generator that generates an initialization signal in response to a specific sequence of reset control signals. A transfer unit activates a reset signal for resetting various circuits on the device in response to either the initialization signal or a conventional power-up initialization signal. Thus, the initialization signal generator provides reliable initialization even if the power-up detection circuit fails. External row and column address strobe signals serve as two reset control signals, while a mode selection signal serves as another reset control signal. The initialization signal is activated when the three reset control signals are activated in the proper sequence, then deactivated when one of the control signals is deactivated.

Abstract: A power supply circuit interrupts power to a load in response to a short-circuit or an open-circuit condition and automatically restores power after a momentary short-circuit. A short-circuit detector monitors the current flowing through the load and generates a short-circuit signal if the current exceeds a predetermined level. An open-circuit detector monitors the load voltage and generates an open-circuit signal if the voltage exceeds a predetermined level. A latch converts the short-circuit signal to a latch signal. A logic unit combines the latch signal with the open-circuit signal and a pulse signal from a pulse generator to generate a drive signal. A driver uses the drive signal to control a switch which is connected between the power source and the load to interrupt power to the load. During a short-circuit, a timer generates a periodic pulse signal that toggles the latch signal and intermittently restarts the power to the load. If the short-circuit was of short duration, power is restored to the load.

Abstract: A charge-pumping circuit of a semiconductor memory device for generating a voltage higher than an applied supply voltage, including a first MOS transistor having gate and drain terminals through which the supply voltage is received and a source terminal through which an initial voltage is provided to a first node; a first capacitor with predetermined capacitance having one plate connected to the first node and the other plate through which an applied first oscillating signal is received; a third MOS transistor having gate and source terminals connected to the first node to introduce the electric current of the first node into its drain terminal; a second capacitor with capacitance lower than that of the first capacitor, having one plate connected to the second node that is the drain terminal of the third MOS transistor and the other plate through which an applied second oscillating signal is received; and a second MOS transistor having drain and gate terminals connected to the first node and the second node e

Abstract: A time-compensated overcurrent detection circuit shuts off a D.C. motor during large overcurrent conditions caused by actual constraints on the motor. The circuit prevents premature motor shut off by establishing a minimum activation time for shutting off the D.C. motor. An overcurrent time compensator establishes a minimum time period for activating a motor reset signal after sensing an overcurrent condition. The circuitry uses a relatively small capacitor that provides quick response to overcurrent conditions.

Abstract: A machine for counting discrete articles, such as tablets, pills, or capsules, comprising a feeder including a hopper for receiving and dispersing a plurality of tablets to be counted into separate streams, a plurality of detectors associated with each stream for detecting each tablet in that stream, a counter coupled to said plurality of counters for counting the total number of tablets in all of the streams and a switching device coupled to each of said plurality of detectors for preventing detector saturation and delay, thereby improving counter accuracy and speed.

Abstract: An internal power supply circuit for a semiconductor memory device comprising a differential amplifier having a reference voltage as an input and utilizing an external power supply voltage. An amplifier output provides an internal power supply voltage. The amplifier is connected to a current source which comprises a plurality of transistors connected in series between one side of said amplifier and ground. A current control transistor having a channel larger than the channels of the transistors connected in series is switchable between a first state in which the current control transistor is substantially on and a second state in which said current control transistor is substantially off.

Abstract: A bit line reference circuit for a nonvolatile semiconductor memory device performs a referenced data access operation using a single bit line having upper and lower portions. The circuit has an open bit line structure and includes an upper memory cell string connected to the upper portion of the bit line, and a lower memory cell string connected to the lower portion of the bit line. An upper reference cell string is connected to the upper bit line for providing a reference potential to the upper bit line in response to a first control signal, while the lower memory cell string is selected. A lower reference cell string is connected to the lower bit line for providing a reference potential to the lower bit line in response to a second control signal, while the upper memory cell string is selected. A page buffer is connected between the upper and lower portions of the bit line and accesses data by comparing the potentials on the upper and lower portions of the bit line.

Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.

Abstract: A dimming control system includes dimmer modules which receive dimming level information from a control module. Each dimmer modules includes a microprocessor which provides internal intelligence for controlling power to a load in response to the dimming level information. The control module receives industry standard protocol dimming information from various sources, converts it to dimming level information, and communicates the dimming level information to the dimmer modules through serial communication lines. The dimmer modules and control module are mounted in a rack which includes a backplane having nonvolatile memory device that retains configuration data even if the control module is removed from the rack. The dimmer modules implement a zero cross prediction method which includes detecting an actual zero cross, calculating an error, and adding the error to the period of a line power signal.

Abstract: The present invention relates to a feedback control system and method for controlling an electronic ballast for driving a lamp where the lamp requires preheating of a cathode of the lamp in order for the electronic ballast to successfully discharge into the lamp and initiate arcing operation in the lamp. The system detects the power consumption level of the lamp and, when the power consumption level indicates that the lamp is not arcing, performs a restart of the lamp wherein the restart function includes preheating the cathode with a preheating current. The present invention reduces production cost and increases safety by detecting operation in the lamp without using external elements.

Abstract: A dynamic display method and apparatus includes a computer operatively connected to an external measuring device (EMD) or numeric input device. A figure approximating a real object or space and incorporating recognizable geometric elements is sketched by the user and displayed on the computer display screen. A specified geometric element of the figure is user selected and dimensioned by operation of an external measuring device. A constraint engine subsystem within the computer incorporates the dimensioning information into the figure and redraws the figure as each dimension is received from the external measuring device.

Abstract: A screening system, preferably a finger screening system, for screening particulate material is provided.

Abstract: A power-up reset signal generating circuit ensures proper operation of an integrated circuit upon power up by inhibiting operation, or forcing predetermined logic states, until the applied power supply voltage reaches at least an acceptable operating voltage level. The present circuit monitors both the supply voltage and a separate back bias voltage that appears in high density integrated circuits such as DRAM circuits. The reset signal initially rises in proportion to the applied supply voltage, and then is pulled down to a logic low level in response to assertion of the back bias voltage, thereby forming a logic transition in the reset signal. Qualifying the reset signal by monitoring the on-board back bias voltage generator ensures that the supply voltage has reached an acceptable operating level, even in circuits where the nominal MOS threshold voltage is reduced, because the reset signal does not change state until the back bias voltage generator is functioning.

Abstract: A frequency modulator controls the center frequency and modulation factor at the same time with one control signal. The frequency modulator includes a voltage-to-current converter that receives an input voltage signal to be modulated, a reference voltage signal, and a control voltage signal, and generates an output current signal by combining the input voltage signal and the control voltage signal. The input voltage signal is amplified by a transconductance amplifier. The control voltage signal is converted into a gain signal which is used to vary the transconductance of the amplifier. A voltage controlled oscillator generates a frequency modulated signal responsive to the output current signal. The center frequency and modulation factor can be controlled by adjusting the value of a resistor in the current-to-voltage converter, a capacitor in the voltage control oscillator, or the control voltage signal.

Abstract: In a semiconductor memory integrated circuit device, power consumption and clock noise are reduced by providing a plurality of separately controlled internal clock signal generators. All of the internal clock signal generators receive an external clock signal, so as to provide respective internal clock signals that are synchronized with the external clock signal. However, each of the internal clock signal generators is separately controlled depending upon the present operating mode of the memory, so that individual internal clock signals are generated only when required.

Abstract: A power analysis tool includes a power arc identifier that extracts power arc information from simulation results including the occurrence time of each arc. These occurrence times are then stored in an arc occurrence database on which power analysis can be performed after the simulation has occurred. This allows a user to specify different circuit groupings on which to perform power analysis without requiring the circuit to be resimulated. The tool also includes a power calculator that converts average current, propagation delay, and intrinsic delay stored in a power data library into positive load current and negative load current for a cell. From these currents an "internal cell" current is derived which is related to the two load currents by a formula.

Abstract: In a semiconductor integrated circuit, an internal passive circuit element value, such as a resistance, is permanently configured to a desired value by selectively fusing one or more fusing elements in response to corresponding input signals. An internal monitor circuit determines whether or not all of the requested fusing operations were successfully completed and, if so, permanently inhibits any further fusing operations. The circuit has the advantage of obviating external measurement of the adjusted circuit element value and further obviates the need for application of a lock input signal to inhibit further fusing operations. Accordingly, testing is simplified and the number of external pins is reduced.