Abstract: A method and apparatus are disclosed for generating random numbers using the meta-stable behavior of flip-flops. A flip-flop is clocked with an input that deliberately violates the setup or hold times (or both) of the flip-flop to ensure meta-stable behavior. When a meta-stable event is detected, an output bit is provided as a random bit. An even random number distribution is obtained by “marking” half of the zeroes input to the flip-flop as “ones” and the other half of the zeroes as “zeroes.” In addition, half of the ones are marked as “ones” and the other half of the ones are marked as “zeroes.” The marking signal is uncorrelated to any noise to a high probability using a linear feedback shift register.

Abstract: A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

Abstract: The invention relates to a Sigma Delta A/D converter (2) for generating a N-bits digital output signal (4) on the basis of an analogue input signal (6), comprising a control loop which comprises a quantizer (8) comprising at least a comparator (24.1, 24.2) for generating the N-bits digital output signal (4) and a D/A converter (10) in a first feedback loop (12) of the control loop for generating an analogue version (14) of the N-bits digital output signal (4) on the basis of the N-bits digital output signal (4), wherein the quantizer (8) also comprises an Up-Down counter (26) which is coupled to the comparator (24.1, 24.2), wherein the D/A converter (10) is coupled to the comparator (24.1, 24.2) in a second feedback loop (27) of the control loop.

Abstract: A cache interface circuit includes a processor interface for receiving memory access requests from a processor, and for transmitting memory data back to the processor in response to processor requests. A main memory interface provides for issuing main memory access requests to a main memory and for receiving main memory data in response. A cache memory interface provides for issuing memory access requests to a cache memory, if operating in a cache mode, and for receiving cache memory data in response. A cache-bypass mode-control signal input provides for the processor to indicate a cache-bypass mode in which memory access requests are serviced from the main memory. A power control output provides for switching off operating power to the cache memory in response to a command received at the cache-bypass mode-control signal input that indicates all memory access requests should be serviced from the main memory.

Abstract: A system and method is provided that searches for the frequency and phase of a CDMA transmission in an iterative manner. With its automatic frequency control (AFC) disabled, the receiving system performs a coarse search for the transmitter's CDMA phase at a nominal receiving frequency. When the coarse phase is obtained, the AFC is invoked with a large-range pull-in, to obtain an initial, coarse frequency that is likely to be closer to the transmitter's frequency than the initial nominal frequency. At this coarse frequency, the receiving system repeats its search for the transmitter's CDMA phase, starting at the previously determined coarse phase. Because this second phase determination is conducted in the presence of less frequency error, it provides for a more accurate phase determination. The AFC is again invoked, but with a small-range pull-in, to obtain a finer frequency determination.

Abstract: In a speech coding system with an encoder and a decoder cooperating with said encoder, the speech encoder comprises a pre-processor and an ADPCM encoder with a quantizer and step-size adaptation means, while the speech decoder comprises an ADPCM decoder with similar step-size adaptation means as in the ADPCM encoder and with a decoder, and a post-processor. The quantizer is provided with storage means containing values for a correction factor ?(c(n)) of the step-size ?(n), said correction factor being dependent on the quantizer output signal c(n). The step-size adaptation occurs in accordance with the relation: ? ? ( n + 1 ) = ? ? ( n ) · A · { ? ? ( c ? ( n ) ) if ? ? ? ? ( c ? ( n ) ) < 1 ? ? ( c ? ( n ) ) + b ? if ? ? ? ? ? ( n ) · A · c max < ? max 1 otherwise ? .

Abstract: A first and second signal source are coupled to an analog output in a digital input signal dependent configuration. The signal sources so that a contribution of their source signals adds up in a first or a second direction when the digital input assumes a first or a second value respectively. The source signals counteract each other when the digital input signal assumes a third value. The signs with which the source signals contribute to the analog signal level for the third value are alternated, so that both signs occur substantially equally frequently for each of the signal sources. The spectral density of a deviation signal due to said alternating is concentrated at high frequencies. In an embodiment the spectral density is moved to high frequency by modulating the alternation onto a high frequency alternation that is used to generate return to zero levels between digital input signal dependent levels.

Abstract: A low dropout voltage regulator comprising a series-regulating element (T1) between an input (I) and an output (O) of the voltage regulator, and a differential input error amplifier (1) having a first output (O1) coupled to a control input of the series-regulating element (T1), characterized in that the error amplifier (1) further comprises a second output (O2) coupled to the output (O) via a high-pass filter (5, C1, R1).

Abstract: An MPEG decoding system selectively decodes MPEG enhanced streams, based on a select identification of an enhancement region of a series of image frames. MPEG blocks within the enhancement region are decoded with the enhancement-layer, while blocks outside the enhancement region are decoded at the base-layer. Additionally, the user is provided the option of displaying the series of images in a window that is selectively sized to contain only the enhancement region, or the enhancement region surrounded by a base-layer region, or a custom sized window that may include all or some of the enhancement and base-layer regions.

Abstract: A gamma correction circuit for correcting a digital video signal, the circuit comprising first (6) and second (8) lookup tables for storing discrete output intensity data and the associated slope data of a non-linear transfer function, respectively, for each of the discrete input video signal intensities, an adder (10) having a first input connected to the output of the first lookup table, a multiplier (12) having a first input connected to the output of the second look-up table (8), characterized by a quantizer (4) for providing the most significant bits of the incoming video signal to address the first (6) and second (8) lookup tables and to transfer the corresponding output intensity data to the adder (10) and the associated slope data to the multiplier (12), the quantizer (4) transmitting the remaining least significant bits of the input video signal to the second input of the multiplier (12), the multiplier (12) multiplying the slope data with the remaining least significant bits and feeding the multipli

Abstract: The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a phase/frequency comparator PD, which supplies a regulation signal Tun, which is subjected to pulse width modulation according to the difference observed. The device also includes a current source, which is designed to emit a charge current Ics, with a value which is controlled by the regulation signal Tun. The device further includes a capacitive element Cs, which is designed to generate the control signal Vcnt, under the effect of the charge current Ics. By means of a regulation signal Tun, which has a frequency which is virtually constant, the invention makes it possible to impose high-frequency variations on the control signal Vcnt.

Abstract: A data converter comprises a discrete-time sigma delta modulator e.g. for driving a Class-D power amplifier. The low-pass filter of the sigma delta modulator is modified by adding a suitably positioned pole to lower the oscillation frequency (limit cycle) of the sigma delta modulator in order to obtain increased clustering of the pulses applied to the output of the data converter.

Abstract: A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes. In a preferred low-cost embodiment, a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions.

Abstract: A system is provided for automatically generating ATAP test solutions. The system includes ATAP simulation circuitry, a bus, an ATAP test bench file, an output file, and a test program. The ATAP simulation circuitry is switchably coupled to a selected analog cell having an ATAP for applying analog tests. The bus is coupled with the ATAP simulation. The bus is operative to transmit and receive analog test simulation data. The ATAP test bench file is configured to receive the simulation data. The output file is operative to store the simulation data and deliver the simulation data to the ATAP simulation circuitry. The test program is generated by the ATAP simulation circuitry in the output file. The test program is configured to automatically generate ATAP test benches based upon chip-specific information. A method is also provided.

Abstract: The invention relates to a receiver of signals [S] received from a wireless network, said receiver working at a so-called reference oscillation frequency controlled by a so-called reference value [Vref]. Said receiver includes demodulation means [DEMO] for demodulating the received signal [S], means [EST] of estimating a mean value [MV] of the demodulated signal [SD], means [COR] of correcting the mean value [MV] of the demodulated signal [SD] to the reference value [Vref], decision means [DEC] for determining the binary values adopted by the received signal [S]. According to the invention, the estimation means [EST] include first means [ESTA] of fast extraction of a first mean value [MVA] of the demodulated signal [SD] used in decision means [DEC] during a first time period and second means [ESTB] of slow extraction of a second mean value [MVB] of the demodulated signal [SD] used in correction means [COR] and, during a second time period, in decision means [DEC].

Abstract: For a digital demodulator for AM demodulation of a difference sound signal in a digital multiplex signal, which multiplex signal also comprises a sum sound signal in the baseband position and a pilot carrier at a pilot frequency, and the difference sound signal is modulated on a carrier at twice the pilot frequency, an extremely simple and adjustment-free construction is ensured in that CORDICs (1, 7) are provided which perform a coordinate transformation of polar coordinates into cartesian coordinates and each have a phase input, two amplitude inputs assigned to the coordinates x and y and two outputs assigned to the coordinates x and y, in that a phase-locked loop comprising a first CORDIC (1), a loop filter (2) and an accumulator (4) are provided, which phase-locked loop supplies a phase ramp signal whose repetition frequency is dependent on the input signal of the accumulator, in that the multiplex signal at an amplitude input of the first CORDIC (1), the output signal of the accumulator (4) at the phase

Abstract: In-progress call transfer between a wireless telephone and a wired telephone is effected using a short-range wireless communication link between the devices. Each of the devices are provisioned to include a short-range radio or infrared transceiver so that the devices can communicate with each other over the short-range wireless communication link, preferably using a given short-range wireless protocol. When the wireless telephone's battery is almost exhausted, or for any other reason that the user may desire, the wireless telephone requests the wired telephone's phone number by communicating with wired telephone over the short-range wireless communication link. Upon receipt of the wired telephone's phone number the wireless telephone issues a call transfer request to a cellular base station, passing the wired telephone's phone number. The base station and the network then re-route the call to the wired telephone.

Abstract: The invention provides for a delay fault testing method and related circuitry for producing a test pulse in response to an input clock signal, and including analysing first and second clock signals having different frequencies and associated with logic circuits having different application speeds, generating a train of two clock pulses for each of the said first and second clock signals, the train of clock pulses being arranged such that the rising edges of the second pulses in each of the said trains are aligned.

Abstract: A processing device comprises an instruction memory 120 for storing virtual machine instructions, such as Java byte codes. A processor 112 of the processing device comprises a predetermined microcontroller core 114 for executing native instructions from a predetermined set of microcontroller specific instructions. The native instructions differ from the virtual machine instructions. The processor 112 is of a type which may request re-feeding of a plurality of native instructions. For instance, the processor 112 may have a pipeline and/or instruction cache which after an interrupt need to be re-filled. The processing device comprises a pre-processor 130 with a converter 132 for converting at least one virtual machine instruction, fetched from the instruction memory, into at least one native instruction.

Abstract: The reconfigurable analog cell according to the invention comprises admittances yab having first terminals (a) which are coupled to first terminals SW1 of a first plurality of switches, and having second terminals which are coupled to the first terminals SW1 of a second plurality of switches. The switches having second terminals, wherein each one of the second switch terminals SW2 of the first plurality of switches and of the second plurality of switches is coupled to at least one node of a plurality of nodes. In the arrangement only one of the switches from any plurality is ON. Therewith a particular state of a plurality of possible states (PSPPS) of the RAC (100) is defined, each of the states defining a transfer function having the same set of poles.