Abstract: A speech enhancement system for the reduction of background noise comprises a time-to-frequency transformation unit to transform frames of time-domain samples of audio signals to the frequency domain, background noise reduction means to perform noise reduction in the frequency domain, and a frequency-to-time transformation unit to transform the noise reduced signals back to the time-domain. In the background noise reduction means for each frequency component a predicted background magnitude is calculated in response to the measured input magnitude from the time-to-frequency transformation unit and to the previously calculated background magnitude, whereupon for each of said frequency components the signal-to-noise ratio is calculated in response to the predicted background magnitude and to said measured input magnitude and the filter magnitude for said measured input magnitude in response to the signal-to-noise ratio.

Abstract: An electronic device has a plurality of subdevices with each subdevice coupled to a test interface. The test interfaces are arranged in a chain of test interfaces by coupling the TDO contact of a predecessor test interface to the TDI contact of a successor test interface in the chain. In addition, at its beginning, the chain is extended with a boundary scan compliant test interface for testing other parts of electronic device. Both the TDO contact of the last test interface in the chain as well as the TDO contact of test interface are coupled to a bypass multiplexer, thus yielding two possible routes from test data input to test data output: through the full chain or through test interface only. Consequently, electronic device can be tested or debugged as a macro device or as a collection of subdevices.

Abstract: The invention relates to a Polyphase-Notchfilter for filtering input signals comprising known bandpass filters, which comprise voltage-controlled current sources. To provide an integrated circuit that has notch filter functionality with reduced circuit erogation, that allows high suppression with little matching effort and reduced power consumption it is proposed that at least two second voltage-controlled current sources are provided, that said at least four input means are coupled to said at least two second voltage-controlled current sources, and that said at least four output means are coupled to said at least two second voltage-controlled current sources, and that said at least one second voltage-controlled current sources are coupled antiparallel to bandpass filter.

Abstract: According to the invention, a circuit arrangement for gaining a 38 kHz stereo subcarrier and a 57 kHz RDS carrier for decoding a stereo signal comprised in a demodulated FM signal and/or an RDS signal comprised in a demodulated FM signal, having a simple structure with only one PLL and particularly only one voltage-controlled oscillator (2) is characterized in that the arrangement comprises a phase-locked loop with a loop filter (1), a voltage-controlled oscillator (2), a first phase detector (3) which receives a reference signal having a reference frequency, and a second phase detector (4), which receives the FM signal, the output signal of the voltage-controlled oscillator (2) being coupled to both phase detectors (3, 4) in a form divided down by means of dividers (6, 9; 10, 11), and the signal fed back to the second phase detector having a frequency of 19 kHz, in that dividers (9, 10, 12) are provided, by means of which the output signal of the voltage-controlled oscillator (2) is divided down and which su

Abstract: An arrangement for selecting the largest of a plurality of input currents (pma (k?1), pmb (k?1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.

Abstract: A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear.

Abstract: Access by a function to a collective resource is controlled by requiring that the function waits for a minimum number of clock cycles CLK called latency [LAT] between two successive accesses of the function. The function is further required to wait a number of cycles called penalty [PEN] which is higher than the latency between two successive accesses when a given number of successive accesses separated in time by at least the value of the latency has taken place beforehand. Registers [REG1, REG2] are decremented (or incremented) with each clock cycle and incremented (or decremented) with each access of the function to the collective resource. Tests [T1, T3, T4] are made with the contents of the registers to authorize [GRT] the access to the collective resource.

Abstract: A method for transferring data on the fly between an RGB color space and a YCrCb color space useful for a DCT block-computation engine significantly increases throughput and decreases processor overhead. According to one example embodiment, data is transferred from an RBG color space memory to a YCrCb color space memory in a form useful for presentation to a DCT block-computation engine. In response to accessing the RBG color space memory, the RBG values are asynchronously written to YCrCb intermediate buffers so that one of the YCrCb intermediate buffers is filled through sub-sampling in a manner useful for the DCT block-computation engine while another of the YCrCb intermediate buffers is still being filled. The DCT block-computation engine then accessed the filled YCrCb intermediate buffers while the other of the YCrCb intermediate buffers continues to collect RGB values from the RGB color space memory for the next DCT computation.

Abstract: Digital circuitry is tested through effecting a paired data loop-back from a first buffered output to a first buffered input whilst within the circuitry executing at least part of the test through using a Built-In-Self-Test methodology. In particular, the loop-back is effected from the first buffered data output to a buffered control input, from a buffered control output to the first buffered data input, or both. Advantageously, the buffering is associated to executing a conversion between a digital full swing internal signal and an analog low swing external signal with respect to core circuitry of the digital circuitry.

Abstract: A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

Abstract: An information processing system has first and second physical components represented by a first and second software objects. Both objects have properties that are changeable through calls to the objects. The system enables registering a property route linking a first property of the first object to a second property of the second object so that a change in the first property causes the second call being issued to the second object upon invoking the property route. The input call to the first object comprises an identifier enabling to conditionally invoke the route. In this manner, routes belonging to different scenarios are being kept independent so that the system operates more reliable that without scenario identifiers.

Abstract: Methods and apparatus are described for time-correct combination of two data streams, particularly video data streams. In this case, a sync signal of the first video data stream is a horizontal sync signal. In this case, methods and apparatus are provided to combine the two video data streams in a pixel-precise manner, even though time base error, i.e. discontinuities occur in the second video data stream.

Abstract: A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.

Abstract: The invention relates to a control means for controlling burst accesses to a synchronous dynamic semiconductor memory device comprising at least two memory banks. In order to avoid relatively large time losses due to preparation cycles (precharge and activate), the invention provides an address converter unit (12) for converting a logical access address into physical access addresses by splitting the burst access into at least two partial burst accesses, wherein a first physical access address addresses a first memory area of a first memory bank for a first partial burst access and wherein a second physical access address addresses a second memory area of a second memory bank for a second partial burst access.

Abstract: A filter for processing frequency signals, preferably received, particularly digital television signals is described, which filter comprises a Chebyshev filter (11, 12), a subsequent all-pass filter (13) and a control device (14 to 20) for controlling the Chebyshev filter (11, 12) and the all-pass filter (13).

Abstract: An interpreter uses a symbol table containing information for resolving symbolic references in instructions. Memory is provided for storing symbolic reference-result associations, the result of the association having resulted from resolving the symbolic reference of the association for an instruction. The memory is organized in groups of locations, each for results for a different category of instructions. During execution of a particular instruction, that group is consulted which is assigned to the category to which the particular instruction belongs. If that group contains an association for the symbolic reference in the particular instruction. If there is such an association, the result from the association is used as operand data for executing the particular instruction. If there is no such association, the particular symbolic reference is resolved by means of the symbol table.

Abstract: DVD data is read from an optical disc. Double buffering is used for outer error correction syndromes, the syndrome for one ECC frame being accumulated in one syndrome buffer, while error correction calculations for preceding data block are performed using a syndrome accumulated previously in another syndrome buffer). The syndrome buffers are used in alternating fashion as further blocks of data are received, while the flow of data to a main buffer is uninterrupted. This reduces buffering requirements in the decoder, and relaxes time constraints on the error correction calculations. A multi-beam implementation is disclosed, providing higher throughput.

Abstract: A data processor that can perform instructions in parallel on respective fields in an operand includes a respective multiplexer for each of the respective fields. Each respective multiplexer is controlled by condition data for a particular field, preferably from an addressable storage unit. The condition may take three or more values for each field, which allows multiplexing between three or more values, reflecting a less than, equal to, or greater than relation between respective compare inputs. The inputs of the multiplexers can share read ports to a register file with more than one functional unit connected to only two read ports.

Abstract: A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor is connected to a bus, and the data processing device comprises at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected.

Abstract: To provide a digital signal combining circuit having a function to combine two digital signals converted from two analog signals and a function to compensate for nonlinearity of two A/D converters upon input of one analog input signal and to convert the analog input signal to a digital signal with S/N ratio improved by about 3 dB. The digital signal combining circuit has a first inversion circuit (3), a second inversion circuit (4), an A/D converter (ADC1), a third inversion circuit (6), a fourth inversion circuit (7), another A/D converter (ADC2), a digital inversion circuit (11) and a digital mixer circuit (10).