Abstract: A multi-beam optical disc system is disclosed for recording on DVD or CD optical discs. Recorded data includes inner and outer error protection codes applied to data blocks having a predetermined size. Each block comprises several sectors. Multi-channel read-out provides in parallel a set of N sub-sequences, without restriction to the block or sub-block boundaries. Sector ID codes are detected within each channel to identify a series of sub-blocks forming a part of a data block and, even in the absence of data from the start of the block, outer error protection circuitry processes the sub-blocks to accumulate a partial error protection syndrome for the block. Upon reaching the end of the block, a syndrome for a next block within the subsequence is accumulated.

Abstract: An instruction execution device and method are disclosed for reducing register write traffic within a processor. The instruction execution device includes an instruction pipeline for producing a result for an instruction, a register file that includes at least one write port for storing the result, a bypass circuit for allowing access to the result, a means for indicating whether the result is used by only one other instruction, and a register file control for preventing the result from being stored in the write port when the result has been accessed via the bypass circuit and is used by only one other instruction.

Abstract: A method for displaying information content enabling user-friendly navigation through content. When the user accesses information content, a cursor is initially positioned such as to indicate an element of information content that was determined from a user's profile. An Internet browser positions the cursor, upon access of a web page, for indicating the hyperlink most frequently requested by the user in given past period.

Abstract: A converter for converting an input voltage (Ui) between a first supply terminal (1) and a second supply terminal (2) to an output voltage (U0), which converter includes switching means (S0) which, in the operating state of the converter, are alternately switched on and off under the control of a control signal (Vcntrl), an inductive element (T) which, in conjunction with the switching means (S0), forms a series circuit which is coupled between the first supply terminal (1) and the second supply terminal (2), a control circuit (CNTRL) for supplying the control signal (Vcntrl), and evaluation means (EVMNS) for evaluating a voltage (US) across the switching means (S0), which voltage (US) exhibits ringing, and for supplying the control circuit (CNTRL) with information causing the switching on of the switching means (S0) during a given valley of the voltage (US) across the switching means (S0).

Abstract: An instruction execution device and method are disclosed for reducing register write traffic within a processor with exception routines. The instruction execution device includes an instruction pipeline for producing a result for an instruction, wherein the exception routines may interrupt the instruction pipeline a random intervals, a register file that includes at least one write port for storing the result, a bypass circuit for allowing access to the result, a means for indicating whether the result is used by only one other instruction, a register file control for preventing the result from being stored in the write port when the result has been accessed via the bypass circuit and is used by only one other instruction, a First in First out (FIFO) buffer for storing the result and a FIFO control for writing the contents of the FIFO buffer to the register file when an exception occurs.

Abstract: A computer system is provided with a memory management unit (MMU) utilizing a translation look-aside buffer (TLB) arrangement. The computer system includes a bus, a unified cache memory, a main memory, a processor, and a memory controller. The TLB is configured for storing code and/or data. The main memory is coupled to the bus. The main memory contains descriptor tables for mapping virtual-to-physical address translations within a virtual memory system. The processor is coupled to the bus and the unified cache memory. The processor is configured to communicate and sequentially move through the main memory to retrieve a line of information from the main memory for storage in the unified cache memory. The cache is configured for storing the most recently retrieved code and data from main memory. The memory controller is coupled between the bus and the main memory.

Abstract: A communication system comprising a power amplifier coupled to a detector and further coupled to a Bias generator. The detector comprises a controlled amplifier means for generating an output signal (Th_S), the said signal Th_S being indicative for the power of an input signal and having a controllable bias level. The Bias Generator comprises a Level Sensitive Current Generator (LSCG) for generating a current (Cc) controlled by the output signal Th_S. Said LSCG has a threshold level (TL) such that when the output Th_S signal is lower than the TL the current Cc is substantially zero. Otherwise the current Cc is linearly controlled by the signal Th_S. The Bias Generator further comprises an adapter coupled to the LSCG comprising a current controlled adapting means for generating a control signal (C_S) for controlling a property of the amplifier, the control signal C_S having a controllable linear dependency on the current Cc.

Abstract: An electronic circuit device has contact terminal outside its package. The contact terminals are connected via the main current channels of two transistors connected in parallel between the contact terminals, so as to provide a switchable short circuit between the terminals. The device is tested by connecting two sense contacts of a resistance measuring device to the terminals and measuring the resistance between the sense contacts a first, second and third state respectively, the first and second transistor being switched on and off respectively in the first state and vice versa in the second state, both transistors being switched on in the third state. The resistance in the three states is modeled as a model resistance composed of a series resistance component in series with a first resistance component, a second resistance component and a parallel arrangement of said first and second resistance component respectively.

Abstract: A built-in self-diagnostic (BISD) memory device includes a two-dimension memory array provided with a redundant memory rows and columns that can be substituted for various ones in the two-dimension memory array by an external repair facility. A stimulus generator outputs multi-address test sequences to the memory array during a test mode. A response evaluator receives responses from the memory. A fault table stores evaluations of the responses, and communicates them to the external repair facility. A repair register indicates which memory columns have been intermediately scheduled for repair by the response evaluator. Column counters each accumulate the number of memory bit faults detected in a respective memory column. All are disposed in a single integrated circuit semiconductor device.

Abstract: A memory device (118) may use a burst access mode to access a number of consecutive data words by giving one read or write command. These data bursts represent non-overlapping data-units in the memory device which can only be accessed as a whole. Because a request for data may contain only a few bytes and can overlay more than one data-unit in the memory device, the amount of transfer overhead is significant. To minimize this overhead a good mapping from logical addresses to physical addresses is important. For the address translation, a logical array is partitioned into a set of rectangles called windows and each window is stored in a row of the memory device. Data request of data-blocks that are actually stored or retrieved, are analyzed during a predetermined period, to calculate the optimal window size. The memory address translation unit (102) performs the analysis and generates the mapping.

Abstract: A processor architecture supports the decoupling of parameters typically associated with branch/jump instructions. Jump instructions are provided that do not contain an explicit destination address and other jump instructions are provided that do not contain an explicit test condition. The processing system provides a “default” value to any control element in the processor that is not expressly controlled by a particular instruction. In the case of a branch or call instruction, the default destination-address provided to effect the branch or call is the destination-address provided by a prior instruction. Subsequent or alternative branch or call instructions branch to this same address until the default address is set to a different address. In like manner, in most cases, the default condition that is used to determine the result of a conditional test, such as a conditional branch, call, or return instruction, is the last condition specified in a prior instruction.

Abstract: An integrated circuit assembly contains a carrier and a semi-conductor integrated circuit chip 10. A current path on the carrier supplies power to power supply connection of the chip. A magnetic field sensor is provided on the carrier in a vicinity of the current path, for sensing a magnetic field generated by a current through the current path. The assembly contains test-accessible electronic interface to the magnetic field sensor, for testing presence of the current. Preferably the sensors are integrated on the carrier by depositing magneto resistive material and patterning the material so as to provide sensors in the vicinity of current paths. Also preferably, the carrier is an interposer 12 with connecting wiring, which is packaged with one or more integrated circuit chips before mounting the interposer on a printed circuit board 19.

Abstract: An exemplary data processing device includes a clock recovery system for locking a clock frequency to time stamps (PCR) of an incoming data stream, e.g. MPEG. The exemplary device uses a free running clock (20) that generates a reference frequency (FREF) from which a desired locked clock frequency is synthesized (25,35) under control of a processing unit (24,34) that compares (241,341) the locked clock frequency to the time stamps (PCR). MPEG audio and video processing clock frequencies are synthesized (25,35) from a free running reference frequency (FREF) and locked to the MPEG time base on basis of time stamps (PCR) provided in the MPEG data stream. Other sub-systems (23,23′) run on frequencies that are not locked to the time base, e.g. simple multiples (22,22′) of the free running reference frequency (FREF).

Abstract: An optical disk data decoder generates estimates of serial input signal values by slicing them into samples. The data sequences contained in each sample are detected. Successive samples are compared and used to increase or decrease the estimates. Such permits the center bit in a string of identical bits to be detected after subsequent bits have already been received and are being processed.

Abstract: A multiple semiconductor chip (multi-chip) module for use in power applications includes at least a power semiconductor chip and a control semiconductor chip mounted on an electrically conductive heat sink. The power semiconductor chip may be a Silicon-On-Insulator (SOI) device and the control semiconductor chip may be a semiconductor device having a substrate connected to ground potential. The power semiconductor chip and the control semiconductor chip are directly mounted on the electrically conductive heat sink without the use of a separate electrical insulation layer in order to obtain a multi-chip module which is simple and economical to manufacture, and which offers superior performance characteristics.

Abstract: A circuit includes a first transistor connected in series to a second transistor. A gate of the first transistor is connected to a source of the second transistor. The gate of the first transistor may also be connected to a load and may not be connected to ground. A gate of the second transistor may be connected to ground. The transistors are preferably formed by silicon on insulator integration technology.

Abstract: A gain-controlled amplifier comprises two signal output stages arranged in parallel to drive an output load in series. A maximum-gain stage provides a maximum of signal gain and the other minimum-gain stage fixes the minimum overall amplifier signal gain. Gain-control input signals differentially applied to the two such stages balance the contributions of the respective gain stages delivered to the common output load. In one aspect, a third shunting transistor is used across the minimum-gain stage. In another version, the output load is a tapped resistor and the respective maximum and minimum gain stages drive different taps.

Abstract: An analog FIR-filter comprising an asynchronous &Sgr;&Dgr; modulator (AM) generating amplitude-discrete time-continuous pulses coupled to a sequence of delay cells (C1 . . . Cn) for delaying the amplitude-discrete time-continuous pulses. One or more output devices (O1, On, S1, Sn, I1, In) for low pass filtering of the delayed amplitude-discrete time-continuous pulses.

Abstract: The present invention relates to an integrated circuit and a method of processing graphic patterns comprising pixels. The circuit (CH) is integrated in a video output co-processor. The circuit comprises, on the one hand, a random access memory (RAM) intended to save the patterns and, on the other hand, extraction means (PE) intended to extract pixels as a function of an indication of the number of bits per pixel from the selected pattern and apply them to encoding means (CM). The pixels are then color-characterized by encoding means (CM) for display on a video screen. The circuit avoids the use of an external memory (SDRAM) and thus cluttering of the passband of the video bus.

Abstract: In an integrated circuit comprising an application circuit (1) to be tested and a self-test circuit (5-16) which is provided for testing the application circuit (1) and comprises an arrangement (5-9) for generating deterministic test samples which are applied to the application circuit (1) for test purposes, the output signals occurring due to the application circuit (1) in dependence upon the test samples being evaluated by means of a signature register (13), an unlimited ON-chip testing possibility of the integrated circuit without additional circuit elements in the application circuit (1) is ensured for test purposes in that the self-test circuit (5-16) comprises a masking logic element (14) which, during testing, blocks those bits of the output signals of the application circuit (1) which, based on the circuit structure of the application circuit (1), have undefined states and applies only the other bits to the signature register (13).