Abstract: A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry.

Abstract: A power semiconductor device is shown to comprise a source region (24) and a drain region (26) disposed in a semiconductor substrate (10). A channel region (30) is disposed inwardly from a gate oxide layer (18) and a gate conductor (20). The device comprises a composite drift region (38) is formed of an n-type region (12) and a gallium arsenide region (36).

Abstract: In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer.Other devices, systems and methods are also disclosed.

Abstract: A non-volatile split-gate memory cell 8 which can be programmed with only a five volt power supply and is fabricated using standard transistor processing methods, comprises a semiconductor substrate 10 with a source 12 and a drain 14 region separated by a channel region 16. A conductive floating gate 18 is formed over a portion 16a of the channel region 16 and separated by a FAMOS oxide 20. A conductive control gate 22 is formed over but electrically insulated from the floating gate 18 and over a second portion 16b of the channel region 16. The control gate 22 is separated from the second portion of the channel 16b by a pass oxide 26 which is thicker than the FAMOS oxide 20. Other embodiments and processes are also disclosed.

Abstract: Generally, and in one form of the invention, an integrated circuit is disclosed for providing low-noise and high-power microwave operation comprising: an epitaxial material structure comprising a substrate 10, a low-noise channel layer 14, a low-noise buffer layer 16, a power channel layer 18, and a moderately doped wide bandgap layer 20; a first active region 24 comprising a first source contact 32 above the wide bandgap layer 22, a first drain contact 36 above the wide bandgap layer 22, wherein the first source contact 32 and the first drain contact 36 are alloyed and thereby driven into the material structure to make contact with the low-noise channel layer 14, and a first gate contact 28 to the low-noise buffer layer 16; and a second active region 26 comprising a second source contact 34 above the wide bandgap layer 22, a second drain contact 38 above the wide bandgap layer 22, wherein the second source contact 34 and the second drain contact 38 are alloyed and thereby driven into the material structure t

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.x Ga.sub.1-x As (106), next annealing out defects with the Al.sub.x Ga.sub.1-x As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.

Abstract: Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter 108, a base 126 and a collector 24 is disclosed, wherein the base 126 is composed of one or more islands 126 of semiconductor material. The one or more islands 126 are formed so that they do not cross any boundaries of the active area 60 of the transistor.

Abstract: A molecular beam epitaxy (MBE) system (10) is provided to grow thin film, epitaxy layers (44, 46, 48, 50) on compound semiconductor substrates (40). A mass spectrometer detector (95) is used to monitor and control the flux from selected sources (21, 23, 25, 27) within the MBE system (10). A uniform layer of indium gallium arsenide (46, 50) may be grown on a semiconductor substrate (40) by controlling the indium flux with respect to substrate (40) temperature and time. An epitaxy layer (46) of indium gallium arsenide with uniform mole fraction concentration and reduced lattice strain is produced.

Abstract: A method of etching Group III-V semiconductor materials wherein a plasma of methane, hydrogen and freon is provided in a reactive ion etching chamber having a semiconductor substrate therein and maintaining the substrate to be etched at an elevated temperature of about 100.degree. C. in vacuum conditions of from about 1 to about 100 milliTorr. The temperature range utilized herein is substantially higher than the temperatures used in prior art reactive ion etching of Group III-V compositions and provides substantially superior results as compared with tests of reactive ion etching using all materials and parameters used herein except that the temperature of the substrate being etched was about 34.degree. C. The amount of methane can be from a flow rate of about 5 zero to about 50 SCCM and preferably about 10 SCCM, the flow rate of hydrogen can be from about zero to about 40 SCCM and preferably about 30 SCCM and the flow rate of freon can be from about 5 to about 50 SCCM and preferably about 17 SCCM.

Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.

Abstract: A flip-chip integrated circuit 1100 having a transistor 1108 formed at a frontside surface of a substrate 1104. An airbridge 1106 may be formed over portions of the transistor wherein a top surface of the airbridge is spaced from the frontside surface by a distance approximately equal to, or greater than, the thickness of the substrate. The circuit may also include a transmission line 1114 at the frontside surface and a heatsink 1102 coupled to the airbridge.

Abstract: A flip-chip integrated circuit having passive 302, 304, 306 as well as active 308, 310 components on a frontside surface of a substrate. The active devices have airbridges which contact a heatsink to provide heat dissipation from the junctions of the devices.

Abstract: In one form of the invention, a bipolar transistor is disclosed, the transistor comprising a GaAs substrate in the (111) orientation 100, and an InGaAs region 106 over the substrate 100, the InGaAs region 106 having a first surface and a second surface, wherein the mole fraction of In in the InGaAs region 106 varies from said first surface to said second surface.

Abstract: In one form of the invention, a method is disclosed for fabricating a semiconductor-on-insulator structure comprising the steps of: forming an insulator layer 22; forming a layer 24 comprising boron (B) on the insulator layer 22; and forming a semiconductor layer 26 on the layer 24 comprising B.

Abstract: Generally, and in one form of the invention a method for making a heterojunction bipolar transistor comprising the steps of forming a compound semiconductor material structure comprised of a plurality of layers, wherein at least one of the plurality of layers is comprised of a first material (e.g. GaAs 36) and at least one of the remaining of the plurality of layers is comprised of a second material (e.g. AlGaAs 32); and etching the layers comprised of the first material with an etchant that does not appreciably etch the layers of the second material is disclosed. A surprising aspect of this invention is that no additional etch stop layer was added in the material structure. Etchants were found that stop on the wide band gap emitter layer (e.g. AlGaAs) usually found in heterojunction bipolar transistors despite the similarity of the materials.

Abstract: A method and apparatus for producing photoluminescence emissions (68) from thin CaF.sub.2 films grown on either silicon or silicon/aluminum substrate shows narrow emission linewidth and high emission intensities for CaF.sub.2 with thickness as low as 0,2 .mu.m, The preferred embodiment is doped with a rare-earth such as Nd.

Abstract: A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.

Abstract: A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

Abstract: In one form of the invention, a package for integrated circuits and devices (42), (46) is disclosed, the package including: a package base (44), the base having a first top surface; a layer of material (43) on the first top surface of the base (44) wherein the material (43) is patterned to cover a portion of the base, and wherein the layer of material (43) forms a substrate having a second top surface; a microstrip transmission line (45) on the second top surface; and a plastic encapsulant (50), wherein the encapsulant covers the first top surface of the base.

Abstract: In one form of the invention, an Electrostatic Discharge protection device containing at least one heterojunction transistor is disclosed. In another embodiment, an Electrostatic Discharge protection circuit comprises: a first terminal contact 20; an NPN heterojunction bipolar transistor Q2; a PNP bipolar transistor Q1; a base-emitter shunt resistor R2; an emitter of said PNP transistor connected to said first terminal contact; a base of said PNP transistor connected to collector of said NPN transistor; a collector of said PNP transistor connected to a base of said NPN transistor; and an emitter of said NPN transistor connected to a second terminal contact 22, with said base-emitter shunt resistor connected between said base of said NPN transistor and an emitter of said NPN transistor, whereby a low-capacitance device capable of protecting semiconductor devices from electrostatic discharges in excess of 4000 Volts results. Other devices, systems, and methods are also disclosed.