Abstract: A flip-chip integrated circuit 1100 having a transistor 1108 formed at a frontside surface of a substrate 1104. An airbridge 1106 may be formed over portions of the transistor wherein a top surface of the airbridge is spaced from the frontside surface by a distance approximately equal to, or greater than, the thickness of the substrate. The circuit may also include a transmission line 1114 at the frontside surface and a heatsink 1102 coupled to the airbridge.

Abstract: In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer.

Abstract: In one form of the invention, a circuit is disclosed, the circuit comprising: a transistor Q having an input terminal 14 with an avalanche breakdown voltage to electrical ground; and one or more diodes 16 arranged in a series between the input terminal 14 and electrical ground, the diode series 16 having a forward-biased voltage drop that is smaller than the avalanche breakdown voltage.

Abstract: Generally, and in one form of the invention, a microwave heterojunction bipolar transistor suitable for low-power, low-noise and high-power applications having an emitter, a base 50 and a collector 70 is disclosed, wherein the emitter composed of one or more islands 30 of semiconductor material having a wider energy bandgap than the base 50. The islands 30 are formed so that they do not cross any boundaries of the active area 60 of the transistor.Other devices, systems and methods are also disclosed.

Abstract: Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.

Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semi-conducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

Abstract: A flip-chip integrated circuit having passive 302, 304, 306 as well as active 308, 310 components on a frontside surface of a substrate. The active devices have airbridges which contact a heatsink to provide heat dissipation from the junctions of the devices.

Abstract: A transistor for amplifying a high-frequency signal comprises multiple unit transistors arranged about a center transmission line 122 and features reactive compensation 140 along the transmission line to provide signals at the output of the unit transistors which generally add in-phase. This has advantages in that a larger or more distributed transistor arrangement than can traditionally be used is made possible without incurring the gain or power degradation associated with the phase differences of signals amplified by unit transistors occurring at distant points along the center transmission line. The reactive compensation includes a capacitor 140 at the end of the transmission line 122 that may be fabricated along with the transistor as a portion of a monolithic integrated circuit.

Abstract: A collector-up bipolar transistor having an undercut region (522) beneath extrinsic regions of a base layer (510) and an emitter layer (508). The extrinsic emitter region is depleted of charge carriers and provides passivation for the extrinsic portion of the base layer (508). Contact to the emitter layer may be made by forming contacts on the top surface of the substrate (500) or in a recess in the backside of the substrate.

Abstract: A monolithic circuit including an IMPATT with the IMPATT formed as a plurality of parallel vertical fingers or an array of vertical mesas having a common doped region to apread the area for heat dissipation through the substrate.

Abstract: A power semiconductor device having a source region (24) and a drain region (26) disposed in a semiconductor substrate (10). A composite drift region is formed of an n-type first drift region (12) in the substrate (10) and of a second drift region (36) composed of a second type of semiconductor material such as gallium arsenide or silican carbide which is a different material than that of the substrate.

Abstract: Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.

Abstract: This invention discloses a method to improve significantly the optical properties of rare-earth doped MBE-grown CaF.sub.2 films by annealing such films in a reducing atmosphere (e.g. forming gas) at appropriate temperatures (generally greater than 600 C. Films grown at the same temperature as that used later in the novel annealing process do not exhibit the same PL spectrum nor the high photoluminescence intensity emissions as annealed films. The intensity of the strongest peak 12a in FIG. 2 has a magnitude 3.6 times the intensity than the strongest peak 12 in as-grown film in FIG. 1. Similarly these same films annealed in an oxygen environment do not exhibit the have the desired properties.

Abstract: A molecular beam epitaxy (MBE) system (10) is provided to grow thin film, epitaxy layers (44, 46, 48, 50) on compound semiconductor substrates (40). A mass spectrometer detector (95) is used to monitor and control the flux from selected sources (21, 23, 25, 27) within the MBE system (10). A uniform layer of indium gallium arsenide (46, 50) may be grown on a semiconductor substrate (40) by controlling the indium flux with respect to substrate (40) temperature and time. An epitaxy layer (46) of indium gallium arsenide with uniform mole fraction concentration and reduced lattice strain is produced.

Abstract: A collector-up bipolar transistor having an undercut region (522) beneath extrinsic regions of a base layer (510) and an emitter layer (508). The extrinsic emitter region is depleted of charge carriers and provides passivation for the extrinsic portion of the base layer (508). Contact to the emitter layer may be made by forming contacts on the top surface of the substrate (500) or in a recess in the backside of the substrate.

Abstract: By growing semi-insulating CaF.sub.2 films (296) on a silicon substrate (240), forming superlattice structures (260) made of CaF.sub.2 :Nd and other semiconductor layers (294) and by associating a co-dopant with Nd in the CaF.sub.2 films photoluminescence efficiency of CaF.sub.2 films is increased. This permits using electrons to produce photons and controlling optoelectronic devices using CaF.sub.2 films through voltage variation.

Abstract: A method of etching Group III-V semiconductor materials wherein a plasma of methane, hydrogen and freon is provided in a reactive ion etching chamber having a semiconductor substrate therein and maintaining the substrate to be etched at an elevated temperature of about 100.degree. C. in vacuum conditions of from about 1 to about 100 milliTorr. The temperature range utilized herein is substantially higher than the temperatures used in prior art reactive ion etching of Group III-V compositions and provides substantially superior results as compared with tests of reactive ion etching using all materials and parameters used herein except that the temperature of the substrate being etched was about 34.degree. C. The amount of methane can be from a flow rate of about 5 zero to about 50 SCCM and preferably about 10 SCCM, the flow rate of hydrogen can be from about zero to about 40 SCCM and preferably about 30 SCCM and the flow rate of freon can be from about 5 to about 50 SCCM and preferably about 17 SCCM.

Abstract: A method of fabricating heterojunction bipolar transistors (HBTs) including epitaxial growth of collector, base and emitter layers, allowing for self-aligned emitter-base contacts to minimize series base resistance and to reduce total base-collector capacitance.

Abstract: A circuit for compensating for the phase velocity differences caused by the layout arrangement of a high-frequency transistor circuit comprises a shunt reactive element 60 coupled to an input or output terminal 51 of a first transistor 48 in a sequence of transistors arranged between input 42 and output 54 transmission lines. The shunt reactive element provides adjustment in phase such that signals traversing various routes through the circuit add in phase at the circuit output. The circuit may also include series resonant circuits 102 between the input terminals 44 and 46 of transistors in such a sequence and between output terminals 51 and 52 of transistors in such a sequence. The series resonant circuits appear as short circuits at certain frequencies and thereby may be used to virtually eliminate the phase progression along transmission lines linking transistors in the sequence.

Abstract: This is a p-n junction device and the device comprises: a substrate 10 composed of a semiconductor material; a heavily doped n type sub-collector layer 14 over the substrate; a n type collector layer 16 over the sub-collector layer; a heavily doped p type first base layer 18, over the collector layer; a p type second base layer 20, substantially thinner than the first base layer, over the first base layer, with the second base layer being less heavily doped than the first base layer; and a n type emitter layer 24 over the second base layer, whereby, the second base layer serves as a diffusion barrier between the base and the emitter. Other devices and methods are also disclosed.