Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second element. The memory device may also include logic to detect a destination indication associated with received write data. In some embodiments, the logic determines whether to store the received write data in the first element or the second element based, at least in part, on the destination indication. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the alternating (AC) voltage swing of a CTE to reference voltage.

Abstract: A Seek and Scan Probe (SSP) memory device is disclosed. The memory device includes a moving part having microelectromechanical (MEMS) structures fabricated on a first wafer and CMOS and memory medium components fabricating on a second wafer bonded to the first wafer.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for thermal management using an on-die thermal sensor. In some embodiments, an integrated circuit (e.g., a memory controller) includes temperature collection logic and control logic. The temperature collection logic receives and stores temperature data from a plurality of remote memory devices each having an on-die thermal sensor. In some embodiments, the control logic controls a thermal throttle based, at least in part, on the temperature data. Other embodiments are described and claimed.

Abstract: A method and apparatus for improving printed circuit board signal layer transitions are described. In one embodiment, the method includes the formation of a first via within a printed circuit board (PCB). A second via is formed concurrently within the PCB. In one embodiment, the second via is positioned proximate the first via to enable electromagnetic coupling between the first and second vias. Following formation of the second via, the first and second vias are connected to provide a series connection between the first and second vias. In one embodiment, the series connection between the first and second vias reduces a stub length with respect to the first via to reduce and potentially eliminate stub resonance for, for example, short signal layer transitions. Other embodiments are described and claimed.

Abstract: A network may be abstracted into four layers: a control layer, a network management layer, a verification and validation layer, and a physical network layer. The control layer interacts with the other three layers to execute network scenarios. The network management layer automatically performs network configurations and network transitions to support the network scenarios executed by the control layer.

Abstract: Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not. This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT pin. The integrated circuit also receives, during a second clock, an ODT value selection signal on its ODT pin. In an embodiment, the integrated circuit prevents a reset of the state of the ODT activation signal for a predetermined period of time to enable the multiplexing of signals on the ODT pin. Other embodiments are described and claimed.

Abstract: A system and method for synchronous configuration of DHCP server and router interfaces is disclosed. A network management layer identifies a DHCP server interface and a router interface associated with the same subnet. The network management layer then determines configuration information for the DHCP server interface and the router interface. The DHCP server and the router are programmatically configured with the determined configuration information.

Abstract: A system and method for programmatically changing the network location of a network component is disclosed. A network management layer programmatically interrupts a link between the network component and the network. The network management layer then changes the network to which the network component is linked. The link between the network component and the changed network is programmatically established or reestablished.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.

Abstract: A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams become intermixed, a certain amount of latency results from the resulting page “breaks.” These page breaks occur when consecutive requests are from different data streams, requiring accesses to different memory pages. When several separate streams of data are requested by a client, page coherency between requests diminishes. A reordering device regains lost page coherency, thereby reducing the amount of latency and increasing overall system performance.

Abstract: The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

Abstract: Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.