Abstract: A system and method for prioritizing the transmission of packets in a wireless local area network. A station selects a packet from local priority queuing and identifies the priority bits of the packet. The station declares the priority of the selected packet based on the binary value of the priority bits. If the station detects that another station has selected a packet with a higher priority, then the station ceases to contend for transmission during the current transmission cycle.

Abstract: In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.

Abstract: Methods and apparatuses are described for improving information transfer over a universal serial bus (USB). In some embodiments, an apparatus includes a USB-compliant near-end link and control logic coupled with the USB-compliant near-end link. The control logic may translate a USB-compliant reflective signal received from a USB host to a terminated signal. Other embodiments are described and claimed.

Abstract: In some embodiments, a system includes a cosmic ray detector to detect cosmic rays and to generate cosmic ray detection signals indicative of the detected cosmic rays. The system also includes first circuitry to receive input signals and to produce output signals, and wherein the first circuitry speculates that the cosmic ray detector will not detect cosmic rays, but in response to the cosmic ray detection signals, the first circuitry re-performs at least some operations. Other embodiments are described and claimed.

Abstract: The present invention provides for controlling the order in which packets received from across a network may be processed. A receiver station examines the packets and determines a property of the packet. A priority level is associated with the packet prior to processing. The packet is placed into a queue and processed in an order based at least in part on its priority level. The method may be used to expedite or slow the processing of particular packets, such as advancing the processing order for acknowledgment packets. In addition, other aspects of the present invention relating to determining an order for processing packets by a receiver station.

Abstract: A computer chipset having an identifier module and a router. The identifier module is configured to add sequence identifiers to each transaction in independent ordered sequences of transactions. The sequence identifiers identify which ordered sequence the transactions belong to. The identifier module combines the ordered sequences of transactions into a combined ordered sequence of transactions. The combined ordered sequence of transactions are sent over an ordered interface. A router then separates the combined ordered sequence of transactions into ordered queues based on the sequence identifiers associated with the transactions. The transactions in the ordered queues are executed in an order that reduces the time required to complete the transactions.

Abstract: In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes transmitters to provide transmit signals to chip interfaces and voltage control circuitry to control voltages of the transmit signals. The chip further includes receivers to receive external signals from another chip. The chip also includes evaluation circuitry to determine whether the transmit signals were usable by the other chip based on an evaluation of at least one of the received external signals and to provide a usability indicating signal to the voltage control circuitry indicative of whether the transmit signals were usable by the other chip. Other embodiments are described and claimed.

Abstract: Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved within a certain amount of time. The fetching of this data will cause increased latencies on lower priority clients making requests for data. A method and apparatus for deprioritizing a high priority client is needed to improve the efficiency in handling data traffic requests from both high priority and lower priority clients.

Abstract: Electromagnetic coupling locations are provided along a bus. Devices can be respectively coupled at the locations for communication on the bus. Electromagnetic coupling strengths associated with at least some coupling locations are caused to have different, selected values.

Abstract: In some embodiments, the inventions include a device and bus transaction control circuitry to receive bus transactions with tag space including a first part that at times is used to represent a transaction number and a second part that at times contains information which under some conditions is used by the device. Other embodiments are described and claimed.

Abstract: Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank. The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator's oscillation frequency.

Abstract: An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpolated delay edge while maintaining a substantially constant capacitive loading on the two replica delay edges. The replica delay line may comprise a delay cell of four current-starved inverter delay stages or four capacitor-loaded inverter delay stages.

Abstract: The improved light-emitting device may include a waveguide made with Si nanocrystals doped with optically active elements. The improved light-emitting device may be suitable for use in chip-to-chip and on-chip interconnections.

Abstract: Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.

Abstract: A connector is configured for insertion and removal of a digital device. The connector has contacts arranged to make electrical connection to conductors on the digital device while the digital device is inserted in the connector. A first electromagnetic coupler is connected to at least one of the contacts of the connector. The electromagnetic coupler is configured for electromagnetic coupling at an interface to a second electromagnetic coupler that is connected to a communication bus.

Abstract: An assembly (for example, an assembly in the form of an interposer that is distinct from a motherboard and from the devices that communicate with the motherboard) includes electromagnetic couplings. Each of the electromagnetic couplings couples signals being communicated between a device and a bus. Each of the electromagnetic couplings is connected to (a) an associated bus connector to provide connections of the couplings to the bus, and (b) an associated device connector to provide connections of the couplings to the device.

Abstract: Calibrating return time includes determining clock calibration information based on clock signals local to a master device and return clock signals corresponding to each of at least two slave devices, storing clock calibration information with respect to each of the slave devices with which the master device will communicate using a bus, and, after the clock calibration information has been stored, resynchronizing data signals that are received from each of the slave devices based on the corresponding stored clock calibration information.

Abstract: A method for assigning a device to a first virtual machine includes connecting the device, directly or indirectly, to a computer through an interconnect. The first virtual machine and a second virtual machine are run on the computer. The device is assigned to the first virtual machine for exclusive use by the first virtual machine, and the assignment is enforced.