Abstract: Method and apparatus are described for improving information transfer over USB. In one approach, hub-based extension is realized wherein power is distributed using auxiliary wiring distinct from signal and power wiring present in conventional USB cabling. Additional signals allow optimization of power distribution for powering attached devices, and for detecting and handling illegal connection configurations. In another approach, improvements are realized through use of alternative signaling techniques which eschew reflective and high-speed common-mode signaling. Described are various configuration, media and signal-protocol combinations, including implementations containing embedded hubs. Methods ensuring reliable system behavior are also described, including determination of extension path delay and use of topology-enforcement hubs.

Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

Abstract: At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences occur out-of-phase with at least some of the reference times of another of the sequences. Digital data is encoded onto data signals on one or more communication lines such that a time difference between at least one of the data signals and the nearest one of the reference times on one of the communication lines is smaller than the time difference between the same data signal and the nearest one of the reference times on another one of the communication lines.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated circuit may further include control logic to establish an initial termination resistance during a preamble associated with the command. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

Abstract: An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.

Abstract: The optical modulator may include a strained layer of SiGe to confine carriers in a quantum well. The strained layer of SiGe may be doped with arsenic to provide electrons. The optical modulator may receive an optical signal and modulate the received signal by altering the absorption coefficient of the strained layer of SiGe responsive to an electrical signal. The optical modulator device device may be suitable for use in chip-to-chip and on-chip interconnections.

Abstract: A method and an apparatus for self-heating burn-in have been disclosed. In one embodiment, a semiconductor device includes a plurality of gates, a multiplexer to select a clock signal out of a plurality of clock signals to toggle the plurality of gates in response to the selected clock signal to generate heat internally for burn-in, and a thermal sensing circuitry to monitor an internal temperature.

Abstract: A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.

Abstract: A method and apparatus for initialization of a double-sided memory module having a least one pair of mirrored pins. In one embodiment, the method includes the generation of an opcode to initialize a first side of the memory module according to a first side pin routing. In one embodiment, the opcode is written to a host address selected for the first side of the memory module according to a system host address to memory address mapping. In one embodiment, the opcode is altered if a routing of address pins of the opposed side of the memory module are interchanged with reference to the first side pin routing. Subsequently, a unique host address is selected to produce the altered opcode at the address pins of the opposed side of the memory module according to a defined host address to memory address mapping. Other embodiments are described and claimed.

Abstract: Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

Abstract: In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal. Other embodiments are described and claimed.

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

Abstract: Machine-readable media, methods, and apparatus are described for performing direct memory access (DMA) transfers. In some embodiments, a device may generate an interrupt to request a DMA transfer. A DMA controller may claim the interrupt and may prevent a processor from receiving and/or servicing the claimed interrupt. The DMA controller may further transfer a data block in response to the claimed interrupt.

Abstract: A method and apparatus for booting from a selection of multiple boot images. Control logic is coupled with a plurality of memory devices containing a plurality of boot images. The control logic employs a device select value to map device requests to memory devices. An event agent monitors the apparatus for various events including a corrupted primary boot image. The event agent notifies the control logic when an event occurs and the control logic changes the device select value responsive to the event. The mapping from device requests to memory devices changes when the device select value changes.

Abstract: Various embodiments of the invention relate to an apparatus and method for efficiently implementing out-of-order servicing of read requests originating from an input/output (I/O) interface with minimal additional storage. For example, a number of read entries may be generated from data read requests stored in a first-in-first-out in a first order. The read entries are stored in a storage device and each read entry identifies internal data reads to read data to service the data read request to which the read entry corresponds. A controller coupled to the storage structure may then submit the internal data reads a central arbiter to read data in a second order that is different than the first order. Moreover, the controller also allows the second order to include internal data reads from one read entry, before a completing servicing of another partially serviced read entry, thus providing “simultaneous” servicing of several read entries.

Abstract: A method and apparatus is provided for serial port redirection using a management controller. A serial controller is selectively coupled with a management controller to facilitate the redirection of serial information. The management controller includes a packetizer to packetize the serial information. The packetized information may be communicated to remote computing devices over a network connection or a management bus. The management controller receives both redirection and non-redirection packets from the communication channel. If the management controller receives redirection packets from a remote computing device, it formats the redirection packets as a stream of serial information and communicates the stream of serial information to the serial controller.

Abstract: Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving the other set of address signal lines with the same address, but driven to opposing logic states, to achieve a greater balance between the quantity of signals across both buses that are driven to a high state versus those that are driven to a low state.