Abstract: An error correction method and apparatus for optical disc systems, capable of performing error correction procedures selectively according to the type of optical disc being used, such as CD-DA and CD-ROM, either of which can be used interchangeably in the system. In the method, the first step is to receive old data sequences and old erasure pointers associated with the old data sequences from the optical disc drive. The second step is to decode the old data sequences and the associated erasure pointers so as to generate new data sequences and a set of erasure pointer modification parameters. In the final step, a number of erasure pointers to be associated with the new data sequences are determined based on the set of erasure pointer modification parameters, and by using a first transform method if a first type of optical disc such as CD-DA is being read and a second transform method if a second type of optical disc such as CD-ROM is being read.

Abstract: A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

Abstract: A method of manufacturing epitaxial titanium silicide in a metal silicide processing has a lower than usual processing temperature requirement, and is therefore suitable for use in the manufacturing of integrated circuits. The epitaxial titanium silicide so formed is made without a grain boundary and is thus capable of lowering the electrical resistance of the titanium silicide. First, a silicon substrate with an exposed crystalline silicon layer on the surface is provided. Then a titanium layer and a titanium nitride layer are sequentially formed. Finally, using a rapid thermal processing, an epitaxial titanium silicide layer is formed.

Abstract: A bipolar variable resistance device suitable for integrated circuit applications includes a silicon substrate, and a resistive layer covering the silicon substrate, the resistive layer being doped with impurities of a first polarity and of a second polarity. A dielectric layer covers the resistive layer. A conductive layer covers the dielectric layer. The device is used to change the resistance of the resistive layer by varying a control voltage applied to the conductive layer.

Abstract: A method for downsizing graphic data of a mask pattern stored in a hierarchical graphic database so that the mask pattern can be used in fabrication of integrated circuits (ICs) having a reduced feature size. The method includes filling gaps formed between abutting graphic elements with supplementary graphic elements, without disturbing or modifying the overall hierarchical structure for recording and relating all the graphic elements in the mask pattern. Further, the method downsizes the graphic data of a mask pattern without greatly increasing the amount of required data storage in the hierarchical graphic database, which would burden the storage, transmission, and modification capacities of the mask pattern.

Abstract: A process for forming a narrow field oxide layer with a greater thickness. A silicon substrate is provided on which a layer of pad oxide and a layer of nitride are formed. Then, at least a wide area and a narrow area are defined on the silicon substrate through openings on the nitride layer. A thermal oxidation process is performed so as to grow a first oxide layer on the wide area and a second oxide layer on the narrow area. A polysilicon layer is then deposited over the entire surface. After that, chemical-mechanical polish (CMP) is applied so as to rub away part of the polysilicon layer that is lying above a plane coincident with the topmost surface of the nitride layer, thereby leaving a first polysilicon layer on the first oxide layer and a second polysilicon layer on the second oxide layer. A thermal oxidation process is performed so as to oxidize the first polysilicon layer and the second polysilicon layer, thereby increasing the thickness of the first oxide layer and the second oxide layer.

Abstract: In an instruction prefetch circuit, even when a branch instruction is prefetched, the circuit continues a prefetch operation until branching is actually executed. Accordingly, when the branch instruction is a conditional branch instruction and not actually executed, the circuit continues the prefetch operation so that the prefetched instructions are efficiently supplied to a processor. It may be arranged that, when the branch instruction is an unconditional branch instruction, a branch destination address is extracted from the unconditional branch instruction and used as a prefetch address. Accordingly, the circuit continues the prefetch operation even when branching is executed. It may further be arranged that, when the branch instruction is a conditional branch instruction, a branch destination address is extracted from the conditional branch instruction and further a branch prediction is performed.

Abstract: A multiple chip module for packaging integrated circuit chips. It has a module body with multiple faces and covers. One of the faces has conduction pads. Each of the other faces has a chip receiving compartment. Each compartment includes at least one chip receiving section. The bottom boundary of the chip receiving section faces the center of the module body and each chip receiving section includes a base surrounding its bottom boundary for locating and bonding one of the chips. Conduction areas are provided on the base of each of the chip receiving sections for connecting with the pad windows of one of the chips and are connected with corresponding conduction pads through a layout in the module body. The covers cover the chip receiving compartments for sealing the chips therein.

Abstract: A motion detector and a motion area detector detect shifts of areas at which motions exist by using signals of fields before and after the field to be detected. According to shifts of the detected areas, an initial vector closest to the true motion is selected among prospective initial vectors produced at an initial vector selector or an initial vector detector by a block matching method, thereby reducing detection errors in motion vectors occurring at a time of the detection of motion vectors, and thereby improving accuracy of motion vectors, so that image distortions would be reduced in an interpolating process.

Abstract: A structural configuration for a ceramic ring for guiding a semiconductor wafer down to the lower electrode of a dry etcher having upper and lower electrodes. The ceramic ring includes a base ring, a wall ring rising perpendicular to one surface of the base ring, and more than ten projections located on the top edge surface of the wall ring. Each of the projections includes a first and a second triangular surface, each at one end of the prismatic body and rising from the top edge surface of the wall ring. An inner sloped surface rises from-the top edge surface of the wall ring and an outer sloped surface rises from the top edge surface of the wall ring. First and second oblique sloped surfaces rise from the top edge surface of the wall ring, connecting the first and second triangular surfaces to the inner sloped surface, respectively.

Abstract: A mold for molding a semiconductor package which is capable of guiding a resin material for encapsulating a semiconductor device uniformly into the cavity and prevents the island portion of the support member from being exposed from the molding main body, the mold comprising a pair of mold members for encapsulating a semiconductor device held on the support member, and a gate for guiding a molding resin material into the cavity, the gate being provided in the parting face of parting face of at least one of the mold members, wherein the gate is defined by a U-shape groove including the slanted bottom face inclined at an elevation angle toward the cavity to orient the flow of the resin material, supplied to the gate, toward the half of the cavity defined by the other mold member from the gate, and wherein in the slanted bottom face, there is provided an auxiliary groove for making the resin material, generally guided along the slanted bottom face, partially oriented to a direction different from the direction o

Abstract: A supplementary implantation method for fabricating a twin gate CMOS. A first conductivity-type well region and a second conductivity-type well region, with an isolating region therebetween, are formed on a semiconductor substrate. A gate oxide layer is formed on the surface of the first and second conductivity-type well regions. Next, a polysilicon layer is formed on the surface of the gate oxide layer and is lightly doped with ions of a first conductivity-type. Ions of a second conductivity-type are then implanted in the polysilicon layer above the first conductivity-type well region and thereby convert the layer into a lightly doped layer of the second conductivity-type, while leaving the polysilicon layer above the second conductivity-type well region still lightly doped with the first conductivity-type ions.

Abstract: A linear receiver is disclosed which includes a linear receiver having: a preamplifier for amplifying linearly a modulated carrier signal (RF signal) having a first frequency trapped by an antenna; a mixer for converting the RF signal into an intermediate frequency signal having a second frequency less than the first frequency in accordance with a local oscillation signal; an IF stage for analogue delivering a demodulated output signal by saturatedly amplifying the intermediate frequency signal and for outputting an RSSI signal which indicates a level of the RF signal; an IF stage for digital incorporating therein an AGC input terminal for controlling an amplitude gain thereof for outputting an in-phase (I) signal and a quadrate (Q) signal, respectively, with the intermediate frequency signal by linearly amplifying the intermediate frequency signal; a first feed back loop circuit for providing a first feed back control signal to the AGC input terminal so as to keep demodulation levels of the I signal and the

Abstract: A process for obtaining a motion vector for motion estimation used in a video image analysis, utilizing a block matching algorithm, which has the effect of reducing the computational load that is placed on the hardware logic used for implementation of the process. In a process of obtaining the absolute error value for the compared image block, a preliminary comparison is performed for every processed pixel in the image block to determine if the set minimum value of the absolute error function represented by a motionless tolerance constant is achieved. It is not necessary to obtain every actual value of the absolute error function. The block matching scheme of providing motion estimation enables hardware implementing the process to discontinue processing if the desired motion vector is selected prior to all image blocks being compared.

Abstract: A MOS transistor structure for an electro-static discharge (ESD) protection circuit of an integrated circuit device. The ESD protection transistor has a structure that comprises a drain diffusion region formed in the silicon substrate of the integrated circuit device, a source diffusion region formed in the silicon substrate, a gate formed in the silicon substrate, and a number of isolated islands evenly distributed throughout the drain diffusion region. The isolated islands provide substantially uniform diffusion resistance between the drain contacts and the gate while increasing the diffusion resistance of the drain region to a level suitable for ESD current protection. The disclosed MOS transistor structure may be fabricated by a salicide technology-based fabrication procedure that is completely compatible with the salicide technology used for the making of the circuitry for the IC device.

Abstract: An electrostatic discharge protection network which diverts ESD stress arising between any two contact pads of an IC device, in order to prevent damage to the internal circuitry of the IC device. An ESD discharge bus is arranged around the periphery of an IC chip. Between each IC pad and the discharge bus, there is a protection circuit to directly bypass an ESD stress arising at any two IC pads. Each ESD protection circuit includes a diode, a thick-oxide device, a resistor, and a capacitor. The protection circuit is operated in snapback mode without causing breakdown. Therefore, the triggering voltage of the ESD protection circuit is lowered to the level of the snapback voltage but not to the level of the breakdown voltage.

Abstract: An improved central score block structure for electronic dart games includes a primary score block corresponding to a double bull's eye, a secondary score block corresponding to a bull's eye, and a plurality of resilient elements for supporting respective urge posts of the score blocks. The secondary score block has a slightly tapered central hole having a flanged baffle ring at an outer end. The primary score block is inserted into the central hole of the secondary score block such that its front and rear ends are properly checked by the front and rear ends of the central hole while capable of free displacement therein. The primary score block and the secondary score block will individually respond to a dart hitting the respective rings represented thereby to display the correct score.

Abstract: A structure and a method to increase the capacitance of a DRAM capacitor by forming a capacitor electrode with cellular voids to add surface area. According to the method: a transfer transistor with a gate electrode and source-drain electrode regions is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate and the transfer transistor, and the insulating layer is etched to form a contact void for exposing the surface of one of the source-drain electrode areas as a contact. A first conductive layer is formed on the insulating layer and is coupled to the contact through the contact void. On the first conductive layer, at least one middle insulating layer and one middle conductive layer are formed alternately to construct a multiple layer structure. Within the middle insulating layer(s), intercommunicating voids are formed through which the middle conductive layer is coupled to the first conductive layer is coupled to the first conductive layer.

Abstract: A high-voltage MOS (metal-oxide semiconductor) device and a method for fabricating the same is provided. The high-voltage MOS device features the forming of trench-type source/drain regions by the use of silicon nitride layers to conduct a self-alignment etching process on a polysilicon conductive layer. In addition, an insulating layer is formed between the source/drain regions and the substrate, which prevents the breakdown at the junction between the source/drain regions and the substrate and also prevent the occurrence of leakage current therein. The forming of metal contact windows on the source/drain regions over isolation layers also allows the prevention of over etching, the occurrence of metal spikes, and misalignment of critical dimensions on the substrate. The thus fabricated high-voltage MOS device is therefore more reliable.

Abstract: A signal transmission circuit employing a signal transmitting circuit and a signal receiving circuit. The signal transmitting circuit transfers received signals from an input terminal, through transmission lines, to the signal receiving circuit. The signal transmitting circuit incorporates thereinto a control circuit which operates with the first power source having the first voltage and provides an inverted/non-inverted output in accordance with the first power source, and a pair of the first and the second push-pull type drivers which feed the inverted/non-inverted output from the control circuit. The first and the second push-pull type drivers operate with the second power source having the second voltage lower than the first voltage and transmit complementary transmitting signals having values corresponding to the second voltage corresponding to the input signal driven by the control circuit through the transmission lines.