Patents Represented by Attorney, Agent or Law Firm Randy W. Tung
  • Patent number: 6433427
    Abstract: A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: August 13, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Enboa Wu, Tsung-Yao Chu, Hsin-Chien Huang, Chung-Tao Chang
  • Patent number: 6429523
    Abstract: A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corp.
    Inventors: Panayotis Constantinou Andricacos, Cyril Cabral, Jr., John Michael Cotte, Lynne Gignac, Wilma Jean Horkans, Kenneth Parker Rodbell
  • Patent number: 6425497
    Abstract: A method and apparatus for dispensing a resist solution used in a semiconductor device manufacturing process senses the presence of air bubbles in the solution during delivery through a line feeding a dispensing pump. Air bubbles in the line are sensed by an optical photocoupler that senses changes in the intensity of light refracted through the solution caused by air bubbles entrapped in the solution. The sensor produces an air bubble indicating signal that can be used to activate an alarm or to stop the dispensing process.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: July 30, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yiau-Yi Chu, Jen-Sen Huang, Shih-Hung Lu, Tzung-Chi Fu
  • Patent number: 6426542
    Abstract: An improved diode or rectifier structure and method of fabrication is disclosed involving the incorporation in a Schottky rectifier, or the like, of a dielectric filled isolation trench structure formed in the epitaxial layer adjacent the field oxide layers provided at the edge of the active area of the rectifier, for acting to enhance the field plate for termination of the electric field generated by the device during operation. The trench is formed in a closed configuration about the drift region and by more effectively terminating the electric field at the edge of the drift region the field is better concentrated within the drift region and acts to better interrupt reverse current flow and particularly restricts leakage current at the edges.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: July 30, 2002
    Inventor: Allen Tan
  • Patent number: 6426241
    Abstract: A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Steven A. Cordes, Peter A. Gruber, James L. Speidell, Wayne J. Howell, Thomas G. Ference
  • Patent number: 6425191
    Abstract: An apparatus and a method for reducing solvent residue in a solvent-type dryer for drying semiconductor wafers have been disclosed. The apparatus is constructed by a tank body, a wafer carrier, an elevator means, a tank cover, a solvent vapor conduit and an exhaust means. The exhaust means is provided for fluid communication with a compartment in the tank cover such that any residual solvent vapor or any organic residue in the compartment left from the wafer drying cycle can be evacuated to a factory exhaust system. The present invention novel method for reducing solvent or organic residue in the dryer can be carried out, after the removal of the dried wafers from the dryer, by evacuating the compartment in the tank cover for a time period of between about 30 sec. and about 300 sec. until all residual solvent vapor or organic residue is evacuated.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: July 30, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Rong-Hui Kao, Ming-Dar Guo, Jih-Churng Twu, Tsung-Chieh Tsai, Chia-Chun Cheng
  • Patent number: 6426283
    Abstract: A method for bumping and backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface of the wafer is disclosed. In the method, a preprocessed wafer that has a multiplicity of bond pads formed on a top surface is first provided, a under-bump-metallurgy (UBM) layer is then sputter deposited on top of the wafer surface, followed by the lamination of a dry film resist layer on top of the UBM layer. The dry film resist layer is then patterned with a multiplicity of openings exposing the multiplicity of bond pads, followed by the deposition of a solder material into the multiplicity of openings to form the solder bump's. A protective tape is then adhesively bonded to the top of the dry film resist layer before the wafer is positioned into a backlapping apparatus for removing of a preselected thickness from the backside of the wafer.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: July 30, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yen-Ming Chen, Kuo-Wei Lin, Cheng-Yu Chu, Fu-Jier Fan, Yang-Tung Fan, Chiou-Shian Peng, Shih-Jane Lin
  • Patent number: 6426590
    Abstract: A planar color lamp powered by field emission nanotube emitters and a method for fabricating such lamp are provided. The planar color lamp is constructed with a lamp chamber having at least three spaced-apart, serpentine-shaped emitter stacks formed on a base plate, and at least three spaced-apart, serpentine-shaped fluorescent coating strips formed on a cover plate wherein each of the fluorescent coating strips emits a primary color of red, green or blue when activated by electrons emitted from the nanotube emitter stacks. The nanotube emitter stacks can be advantageously formed by a low cost, thick film printing technique with a material of a mixture of a polymeric binder and nanometer dimensioned hollow fibers such as carbon, diamond or diamond-like carbon material. The present invention planar field emission color lamp provides the advantages of a backlight and color filters into a single compact package that can be fabricated at low cost.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: July 30, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Feng-Yu Chung, Wen-Chun Wang, Kuang-Lung Tsai
  • Patent number: 6423646
    Abstract: The present invention discloses a method for simultaneously removing from a silicon surface polymeric films and damaged silicon layers by exposing the surface to a cleaning solution that contains amine or ethanolamine for a length of time that is sufficient to remove all such unwanted materials. The method is effective in cleaning away damaged silicon layers having a thickness between about 20 Å and about 60 Å in a period of time between about 2 minutes and about 20 minutes. In a preferred embodiment, the cleaning solution is a water solution of ethanolamine and gallic acid.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: July 23, 2002
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tzu-Shih Yen, Hsiu-Lan Lee, Pei-Wen Li
  • Patent number: 6422824
    Abstract: A getter assembly for use in a vacuum display panel is described. The novel getter assembly can be provided including both a non-evaporative getter and an evaporative getter which are uniquely positioned juxtaposed to each other such that ions emitted by the evaporative getter upon activation substantially shield the non-evaporative getter so that gases emitted by the non-evaporative getter when activated does not affect the state of vacuum in the vacuum display panel. A preferred embodiment of the present invention novel getter assembly is shown for vacuum display panels that have sufficient thickness in the cavity so that the getter assembly can be installed inside the cavity.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: July 23, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Chung Lee, Ruey-Feng Jean
  • Patent number: 6424583
    Abstract: A BIST controller and a separate measurement circuit are used to determine the maximum time period for accessing data stored in an embedded integrated circuit memory. The BIST controller includes a finite state controller for controlling the state of said BIST, a pattern generator for generating a patterned stimulus to be applied to the memory, and a comparator for comparing the response of said memory to said stimulus, to a reference response. The measurement circuit includes a pair of logic circuits for respectively operating on “1's” and “0's” data read from the memory, and a plurality of time delay elements that introduce time delays in the data prior to delivery to the logic circuits.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Nai-Yin Sung, Tsung-Yi Wu, Meng-Fan Chang, Hsien-Te Chen
  • Patent number: 6423175
    Abstract: An apparatus and a method for reducing particle contamination by a polymeric film in a plasma etcher are described. In the apparatus for dry etching a wafer, a wafer holder and a ring member positioned juxtaposed to the holder are provided wherein the ring member is used to confine a plasma cloud generated in the chamber cavity onto an exposed surface of the wafer. The ring member has surface areas that is substantially exposed to the chamber interior, the surface areas are roughened to a depth between about 1 &mgr;m and about 10 &mgr;m between peaks and valleys formed in the roughened surfaces by either a sand-blasting method or by a chemical etching method. When the sand-blasting method is utilized to roughen the surface of the ring member, i.e., a focus ring in a reactive ion etching apparatus, particles having a mesh size between 200 mesh and 80 mesh may be suitably used.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yu Chih Huang, Cherng Chang Tsuei, I Chang Wu
  • Patent number: 6423640
    Abstract: A method for planarizing an oxide surface and removing dishing or erosion defect from a semiconductor wafer. An apparatus for carrying out the planarization process on a semiconductor wafer is further described. In the method, a wafer that has metal residues or dishing or erosion defect after a copper CMP process is first rotated at a rotational speed of at least 1000 RPM, while simultaneously a solvent/abrasive particles mixture is injected onto the rotating surface for a sufficient length of time until the metal residues, the dishing or erosion defect is removed. The rotational speed of the semiconductor wafer can be suitably controlled in a range between about 1000 RPM and about 10,000 RPM. For the removal of an oxide layer, a suitable solvent of diluted HF and a suitable abrasive particle such as aluminum oxide may be used.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tze-Liang Lee, Fan-Keng Yang, Chen-Hwa Yu
  • Patent number: 6422610
    Abstract: A deformable fluid supply line for use on a semiconductor fabrication machine is described which includes a generally S-shaped expandable joint connecting between two straight conduit sections for providing full communication thereinbetween and for providing stress absorbing characteristics such that the expandable joint can be stretched or otherwise deformed by at least 2 cm without breaking connections with the two straight conduit sections. When the generally S-shaped expandable joint is provided with a length of at least 10 cm, a deformation of at least 3.5 cm can be tolerated by the expandable joint without causing failure or otherwise damages in the connections with the two straight conduit sections. The deformable fluid supply line can survive an earthquake of the magnitude of Richter 5 scale. The invention further discloses a method for connecting a deformable fluid supply line to a fabrication machine by using an S-shaped joint connected in between two straight conduit sections.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventor: Chi-Wei Chang
  • Patent number: 6424038
    Abstract: Within both a microelectronic conductor structure and a method for forming the microelectronic conductor structure there is employed a silicon carbide layer having formed thereupon a silicon nitride layer in turn having formed thereupon a patterned low dielectric constant dielectric layer in turn having formed interposed between its patterns a patterned conductor layer. Within both the microelectronic conductor structure and the method for forming the microelectronic conductor structure, by employing the silicon carbide layer having formed thereupon the silicon nitride layer in turn having formed thereupon the patterned low dielectric constant dielectric layer, the microelectronic conductor structure is formed with enhanced adhesion and attenuated electrical leakage.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tien-I Bao, Syun-Ming Jang
  • Patent number: 6420703
    Abstract: A method for forming a critical dimension scanning electron microscope calibration standard and standard formed are disclosed. In the method, a plurality of metal lines, i.e. formed of a suitable metal such as W, Pt, Au, Ta or Ti, for use as critical dimension SEM calibration is formed by a focused ion beam technique to produce straight, narrow lines with an edge roughness of less than 30 nm in a 0.5 &mgr;m length. The plurality of metal lines has a line width uniformity of less than 20 nm in a length of 20 &mgr;m.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: July 16, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chia-Fang Wu, Ming-Chun Chou
  • Patent number: 6405994
    Abstract: A flow control valve which does not utilize any moving components in the valve is disclosed. In the flow control valve, a valve housing that has a cylindrical-shaped wall is first provided. Inside the valve housing, is then provided a first and a second end plate for sealingly engaging an inner periphery of the valve housing. The first and the second end plate are positioned spaced-apart in a predetermined distance while each of the end plates has at least one aperture therethrough for the passage of a fluid flow to be controlled. Inside a valve cavity formed between the two end plates and the inner periphery of the valve housing is positioned an inflatable bag such that when a fluid is flown into the inflatable bag, the bag inflates to either partially block or completely block the fluid passageway through the valve cavity.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: June 18, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventor: Wei-Chuan Chen
  • Patent number: 6405359
    Abstract: A method for conducting backside failure analysis on a wafer that only requires simple bias conditions to be fed into defective IC dies and a wafer test specimen which enables such test are disclosed. In the method, a wafer can be first provided that contains at least one defective IC die in an active (or front) surface, at least two conductive metal strips formed of a metal foil are then adhesively bonded to the active surface of the wafer juxtaposed to the at least one defective IC die. At least two lead wires are then bonded by a wire bonding technique between the at least two conductive metal strips and at least two bond pads on the defective IC die for establishing electrical communication therein between. A bias voltage such as a VCC signal or a clock signal can then be fed to the defective IC die through the at least two conductive metal strips, while the defect being observed from the backside of the wafer with an optical detector.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: June 11, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Fouriers Tseng, Thomas Hung
  • Patent number: 6403386
    Abstract: The present invention provides a method for identifying failure sites on a defective IC chip by utilizing a glass substrate equipped with a heating device and then coating a liquid crystal material layer on top. The liquid crystal device can be positioned in contact, or immediately adjacent to a surface of an IC device to be detected. After the liquid crystal temperature is raised to just below its transition temperature, a voltage signal can be fed into the IC device to trigger an overheating at a short or leakage to raise the liquid crystal material immediately adjacent to the short or leakage to a temperature above its transition temperature. Hot spots are thus produced to appear as bright spots for easy identification under an optical microscope.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: June 11, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventor: Chin-Kai Liu
  • Patent number: 6401361
    Abstract: An apparatus for drying semiconductor wafers in a solvent drying chamber and a method for drying are disclosed. The apparatus is equipped with an alarm/interlocking system such that when a flow of the solvent vapor into the drying chamber is stopped, the alarm is triggered and the interlocking system is activated to stop the further loading of wafers into the drying chamber and thus preventing the outputting of undried wafers from the chamber. The apparatus is used to prevent any malfunction in the flow control valves or in any other flow control system that stops the flow of solvent vapor into the drying chamber.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: June 11, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Cho-Ching Chen, Shin-Shing Yang, Jenn-Wei Ju, Liang-Yi Chou, Chih-Hong Cheng