Abstract: Disclosed is a method of allowing a user to assign I/O cells of an integrated circuit chip to package channels of a package, comprising: calculating package RLC values for each package channel in the package; and assigning each I/O cell to one or more package channels based on the calculated package RLC values of the package channels.

Abstract: A method and system for increasing compression efficiency of a lossless data compression utility. The data compression utility compresses a segmented input data stream into independently decompressible data blocks, and includes a history buffer that maintains a history of matching character sequences. In accordance with the method of the present invention, a data segment is compressed utilizing a history buffer to identify repeated character sequences within the data segment. Upon receipt of a next data segment to be compressed, the history buffer is updated to include a pre-selected data set and reset data from the next data segment. As part of the compression an adaptable cache is searched for non-repeating bytes within a next data segment. Matching bytes are coded as cache references. Further efficiency is obtained by processing the next data segment as two-byte pairs.

Abstract: A method of extending a cache of a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. A value is loaded from system memory into one or more caches of adjacent processing units, and when a requesting processing unit issues an inquiry onto the system bus to read the value, the value is sourced from the cache of the adjacent processing unit containing a copy of the value that was most recently accessed. Each cache has at least one cache line with a block for storing the value, and an indication is provided that a cache line having a block which contains an instruction or data is in a “recently read” state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states).

Abstract: A method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal.

Abstract: The present invention is a method and apparatus for generating the second phase (i.e. software for which redistribution rights are limited) of a preload image for networks. The reseller is not required to answer numerous and often repetitive prompts for each application, but merely the location of the desired application.

Abstract: A variable-frequency digital ring oscillator provides small and consistent frequency adjustments throughout a locked range. The ring oscillator of the invention is standard cell placeable and operates at the technology limits to provide small and precise delay changes that is inexpensive to implement. The digital variable-frequency ring oscillator includes multiple macro delay elements forming an inverter ring circuit, each element having an individual macro delay unit that in turn is comprised of multiple adjustable delay units. All of these adjustable delay units are controlled by a single delay control signal.

Abstract: A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.

Abstract: A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers the full width of the device and takes current out of the source in a primarily vertical direction.

Abstract: A method and device for A pass transistor device which includes a source; a drain opposite the source, a body between the source and the drain, and a circuit control network connected between the drain and the source, wherein the circuit control network controls a potential voltage of the body and provides overvoltage protection to the pass transistor.

Abstract: In parallel-serial architecture based networks that include a transmission media and at least one I/O processor connected to the transmission media by a core, a buffering device is provided that compensates for different latencies from all physical lanes in data links so that data transmission occurs at the same time in the receive path of the I/O “processor.” The processor can be an I/O device for a host channel adapter, a target channel adapter, or an interconnect switch in an InfiniBand-type network.

Abstract: A flip-flop circuit comprising: a master latch circuit; a slave latch circuit coupled to the master latch circuit; and a correction circuit for increasing an amount of charge that can be absorbed by the master latch circuit in response to a soft-error event when the slave latch circuit is in a transparent phase and when both the master and slave latch circuits are storing the same data.

Abstract: A flash analog to digital converter includes a reference ladder, consisting primarily of resistors, a plurality of comparators, each coupled to a different reference voltage on the reference ladder (the comparators compare a received voltage with a reference voltage level developed across corresponding resistor or group of resistors), and a variable power source coupled to the reference ladder for varying the reference levels generated from the ladder. The structure includes a fixed (or variable) gain driver supplying the received signal voltage to the bank of comparators. The variable power source can be an adjustable current source or an adjustable voltage source. The comparators can be single-ended comparators or differential comparators.

Abstract: A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

Abstract: A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.

Abstract: An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.

Abstract: A method and system for creating a worst case scenario model for a given integrated circuit. The method comprises the steps of sorting skew parameters of each device into groups; and assigning a positive or negative value for each one of the groups to represent the effect of the corresponding skew parameters on the functionality of the integrated circuit. The preferred embodiment of the invention provides some of the benefits of both conventional corner simulation and Monte Carlo simulation. This approach can be implemented with only a few additional simulation iterations, which mitigates the disadvantage of Monte Carlo simulations requiring many simulation iterations. Also, this approach allows a greater degree of flexibility with respect to determining a specific corner file definition, allowing the designer to explore a greater area of model parameter space to insure that the circuit will meet performance requirements over extremes of process technology variation.

Abstract: A method and structure for calibrating an analog to digital converter comprises an input signal; a driver receiving the input signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2n−1 digital outputs; an encoding logic unit encoding the comparison result into n digital bits as an output signal; a calibration engine outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit receives the reference adjust signal, wherein the calibration engine receives n digital bits, and controls an operation of the driver or flash circuit based on the output signal.

Abstract: The present invention provides a performance based system and method for dynamic allocation of a unified multiport cache. A multiport cache system is disclosed that allows multiple single-cycle look ups through a multiport tag and multiple single-cycle cache accesses from a multiport cache. Therefore, multiple processes, which could be processors, tasks, or threads can access the cache during any cycle. Moreover, the ways of the cache can be allocated to the different processes and then dynamically reallocated based on performance. Most preferably, a relational cache miss percentage is used to reallocate the ways, but other metrics may also be used.

Abstract: The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.

Abstract: A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.