Abstract: A system and method for achieving self-regulated voltage division among multiple serially stacked voltage planes. The system of the present invention is incorporated within a source voltage plane having a source supply node for supplying current and a source ground node for sinking current supplied therefrom. An intermediate voltage supply node is coupled between the source supply voltage node and the source ground node for dividing the source voltage plane into a plurality of intermediate voltage planes. The self-regulated voltage divider of the present invention includes a first capacitor and a second capacitor that are each controllably coupled between either the source supply voltage node and the intermediate voltage supply node, or between the intermediate voltage supply node and the source ground node, such that a voltage level balance is achieved among the intermediate voltage planes.

Abstract: A clock generator having a deskewer is disclosed. The clock generator includes a waveform generator and a deskewer. Clocked by an input clock signal, the waveform generator generates a waveform signal. The deskewer circuit, which is connected to the waveform generator, gates the waveform signal from the waveform generator with the input clock signal to produce an output clock signal such that the output clock signal has less skew with respect to the input clock signal.

Abstract: A digitally controlled oscillator includes an adjustable signal generating circuit adapted to generate an oscillation signal. A feedback loop receives the oscillation signal from the adjustable signal generating circuit. The feedback loop detects error in the oscillation signal and produces an error signal based on the error. The control logic circuit receives the error signal from the feedback loop and maintains the oscillation signal within a predetermined error range. Also, a state device that is connected to the adjustable signal generating circuit maintains a previous operating state of the adjustable signal generating circuit when the digitally controlled oscillator is temporarily powered down.

Abstract: An analog-to-digital converter includes a plurality of comparators that each have an output, two analog data inputs coupled to a differential analog data input, and two reference voltage inputs. The two reference voltage inputs are each coupled to a resistor ladder that contains a plurality of resistors coupled in series. Importantly, the two reference voltage inputs of each comparator are positively biased, meaning that the positive reference voltage input is coupled to a point on the resistor ladder at a relatively higher potential than the negative reference voltage input. The outputs of the comparators are coupled to an encoder that encodes signals at the outputs into a digital signal. By positively biasing the differential reference voltage inputs of the comparators in this manner, the differential gain, dynamic voltage range, and voltage symmetry of the comparators are advantageously improved.

Abstract: A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.

Abstract: A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.

Abstract: A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.

Abstract: A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

Abstract: A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

Abstract: A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.

Abstract: The present invention is a method and apparatus for CMP processing that reduces scratching of the insulating film and conductor lines of a wafer. More specifically, the method and apparatus introduce an aqueous solution to the polishing pad and wafer during various intervals of the polishing procedure.

Abstract: A method and structure for an integrated circuit including a differential amplifier having at least two inputs and at least two outputs; a pair of first resistors, each of which is coupled to one of the inputs; a pair of first source followers, each of which is coupled to one of the first resistors; a pair of second source followers, each of which is coupled to one of the out puts; a pair of second resistors, each of which is coupled to one of the second source followers and to one of said inputs; and a gain device connected between the first resistors and the first source followers.

Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices. The differential circuit includes an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.

Abstract: A method of programming a conductive semiconductor device having a plurality of conductive links by selective removal of all or portions of the conductive link using photolithographic and subtractive etching. Removal of only pre-selected conductive links is accomplished by use of a programmable array shutter to expose photoresist only above the conductive links to be removed.

Abstract: A phase-locked loop (PLL) device includes phase error control for allowing quick transitions from a first operating point to a second operating point when the phase error exceeds a user-defined threshold. Phase error control is accomplished by adding an additional charge pump and accompanying user-settable circuitry to the PLL device.

Abstract: An ESD power clamp circuit provides ESD protection for semiconductor chips through a power clamping device. The power clamping device includes a FET and a bipolar element, formed in an isolation region, and a buried diffusion. The buried diffusion is used as a subcollector for the bipolar element, and is used as an isolation for the FET.

Abstract: A bipolar transistor is disclosed. The bipolar transistor comprises: a silicon substrate; a collector formed in the semiconductor substrate, a base formed over the collector, the base having an intrinsic base region and an extrinsic base region, the extrinsic base region forming an internal resistor, an emitter formed over the intrinsic base region; and a dielectric layer formed between the extrinsic base region and the collector, the extrinsic base region. the dielectric layer and the collector forming an internal capacitor. The base of the transistor may be silicon-germanium.

Abstract: A structure for an amplifier circuit which includes a pair of source-coupled differential transistors, each of source-coupled differential transistors having a body and a gate, and input transistors electrically connected to the source-coupled transistors. Also, the input transistors load the body and the gate of the source-coupled transistors with positive feedback signals. As a result, a differential gain is increased and a common mode gain is not increased. The output of the pair of source-coupled differential transistors is directed to second pair of transistors. The second pair of transistors generates mirrored voltages which track with input voltages. The second pair of transistors generates mirrored voltages translated by an offset voltage to values near ground, mirrored voltages which represent a voltage gain over an input voltage, and mirrored voltages which are largely differential and includes approximately no common mode input voltage.

Abstract: A structure and method for reducing bipolar current in of a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source coupled to an inverter and a primary node, further coupled to a first and second PFET device; a clock signal source; coupled to a first NFET device and a third PFET device; a first input signal source coupled to a second NFET device and a fourth PFET device; a first NFET stack node coupled to the third PFET device, the first NFET device, the primary node, and the second NFET device; a second input signal source coupled to a third NFET device; a fifth PFET device coupled to the fourth PFET device; a power supply voltage source coupled to the fifth PFET device; and a second NFET node coupled to the fourth PFET device, the second NFET device, and the third NFET device.

Abstract: A method and apparatus for implementing a dual voltage driver circuit having two predrive circuits for driving the supported voltages. The driver circuit automatically senses the operating voltage and selects the appropriate predrive circuitry while isolating the non-selected predrive circuitry from the sensed voltage.