Abstract: This is a system and method of processing multiple video streams for a computing device. The system may comprise: a central processing device; a communications bus connected to the central processing device; an input device connected to the central processing device by the communications bus; an output device connected to the central processing device by the communications bus; a multiple video stream processor connected to the output device by the communications bus; and at least two video streams connected to the multiple video stream processor. In addition, the video streams may include input from a CD-ROM, PCMCIA cards, storage devices, peripherals on docking stations and other communications devices. Moreover, multiple video processing device may include input from zoom video ports, buffers and digital-to-analog converters, and a reformatting device. Other devices and systems are also disclosed.

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is arranged with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and a single select signal such as an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A microprocessor (5) for coupling to an external read/write memory (20) having an addressable storage space. This storage space stores cacheable digital data and non-cacheable (32) digital data. The microprocessor includes a data storage circuit (62) for storing a portion of the non-cacheable data. The microprocessor further includes an address storage circuit (64) for storing an address corresponding to the portion of the non-cacheable data. Still further, the microprocessor includes a counter (72) for advancing a count from an initial value (74) toward a threshold value (76) in response to an activity over time. The counter initiates its advancing operation in response to the data storage circuit receiving the portion of the non-cacheable data. Lastly, the microprocessor includes an indicator (66) for indicating the portion of the non-cacheable data in the data storage circuit is expired in response to the count reaching a threshold.

Abstract: Serial data processor (16) includes a digital processor (106) , a memory controller (114) interconnected with digital processor (106), and dynamic serial access memory (112) interconnected with memory controller(134) . First data selection circuit (134) sends serial data either from serial-data-in terminal (94), from dynamic serial access memory (112), or from digital processor (106) to second serial-data-in terminal (138), in response to a first control signal. Second data selection circuit (144) sends serial data either from serial-data-in terminal (138), from dynamic serial access memory (132) or from the digital processor to serial-data-out terminal (96), in response to a second control signal. A third data selection circuit (120) sends serial data either from serial-data-in terminal (94) , from dynamic serial access memory (112), or from the digital processor (90) to third serial-data-in terminal (150), in response to a third control signal.

Abstract: A microprocessor with an execution stage (26) including a plurality of execution units and an instruction memory (32) for storing instructions. The microprocessor further includes circuitry for retrieving (14) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (30) for storing a plurality of information fields (30r) corresponding to a branch instruction. The information fields include at least a target instruction address (Tn), a prediction field (Pn) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPAn) indicating accuracy for past prediction fields.

Abstract: A voltage-controlled oscillator (10), which is comprised of two subcircuits (10a, 10b). Each subcircuit (10a, 10b) has a pair of differentially connected transistors (Q1,Q2 and Q3,Q4). The first subcircuit (10a) is an LC oscillation subcircuit, in which each transistor (Q1, Q2) has a capacitive transformer (C11,C12 and C21,C22) in its feedback loop. The second subcircuit (10b) is a current-controlled variable-capacitance subcircuit, whose feedback loop has a gain that determines the effective capacitance of the subcircuit (10b). When the subcircuits (10a, 10b) are combined, the feedback loops on each side of the differential pairs (Q1,Q2 and Q3,Q4) share the capacitive transformer (C11,C12 and C21,C22). The result is that the effective capacitance determines the oscillation frequency for the oscillator (10).

Abstract: Cavities such as vias and contacts formed in semiconductor devices are filled in a multi-stage process to provide low resistance electrical connections. A liner is first deposited into the cavity at a relatively low power and deposition rate to enhance "wetting" of a subsequently deposited fill material. The fill material is deposited at a comparatively greater power and deposition rate to close the mouth of the cavity, after which the fill material is extruded at high pressure into the cavity to substantially fill the cavity. Relatively low processing temperatures and high pressures are utilized to allow for the use of lower dielectric constant dielectrics, which are thermally unstable at conventional processing temperatures.

Abstract: The present invention provides a method of ameliorating the effects of misalignment between modulator arrays, and a system using the same. The ability reduce the effects of misalignment allows multiple, smaller, more cost effective arrays to be used instead of one large array. This can reduce the manufacturing costs of the array, especially arrays that are produced using semiconductor manufacturing processes such as the digital micromirror device. To avoid visual artifacts caused by the misalignment of two or more modulator arrays 1702, 1704, the individual arrays 1702, 1704 are optically overlapped and a portion of the image 1706 is generated by both arrays 1702, 1704. A breakpoint is chosen between two pixels in the overlapped region 1706 at which to abut the images from each of the modulator arrays 1702, 1704. The breakpoint is changed each row of pixels to minimize the detectability of any visual artifact caused by misalignment between the modulator arrays 1702, 1704.

Abstract: A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

Abstract: A driver circuit (12) having a controlled transition rate is provided. The driver circuit (12) includes a first device (56) operable to switch a supply voltage to load. A second device (54) is coupled to an input for the first device (56) in source follower arrangement. A third device (66), coupled to the input for first device (56) and an output for the second device (54), is operable to function as a Miller amplifier in conjunction with the first device (56). A fourth device (152) is coupled to an input of the second device (54). The fourth device (152) is operable to function as a Miller amplifier in conjunction with the first device (56) and the second device (54). A capacitor (68) is coupled between an output for the first device (56) and inputs for the third device (66) and the fourth device (152). The capacitor (68) is operable to function as a Miller capacitor to control transition rates at the output of the first device (56).

Abstract: A process for forming a smooth conformal refractory metal film on an insulating layer having a via formed therein. This process provides extremely good planarity and step coverage when used to form contacts in semiconductor circuits and, in addition, offers improved wafer alignment capability as well as enhanced reliability which result from the smooth surface morphology. The process includes forming contact openings through an insulating layer to a semiconductor substrate; depositing a first blanket layer of titanium using deposition conditions that provide a conformal film that exhibits good step coverage at the contact opening; and forming a second blanket layer of titanium using deposition conditions that provide reduced surface asperity height. The process is ideally suited to forming an electrical interconnection system for semiconductor integrated circuit devices such as static or dynamic random access memories and is particularly useful in VLSI devices that incorporate multiple levels of interconnect.

Abstract: Logic circuitry (70, 80, 90) for performing fault detection in a microprocessor (5) is disclosed. The fault detection logic circuitry (70, 80, 90) may be implemented into a scheduler (50) in a floating-point unit (31). Mask register (M) bit positions (M.sub.0 through M.sub.7) store state information relative to registers (52) or other resources in the microprocessor (5) that is to be interrogated upon scheduling of an instruction. The instruction includes an encoded address communicated on register address lines (SA) that is received by the fault detection logic circuitry (70, 80, 90). Pass gates (72) are controlled by the encoded address on the register address lines (SA) to generate a fault indicator (FLT). Partitioning of the decoding of the encoded address may be utilized for optimization of the fault detection operation.

Abstract: A liquid cooled light pipe is disclosed which allows effective pyrometric temperature measurements using a remote detector. Temperature of the light pipe assembly is controlled and maintained at an approximately constant value in order to establish good long-term temperature measurement accuracy. The temperature-controlled light pipe assembly of this invention can be used for multi-point temperature measurements of a heated body with good spatial resolution for real-time multi-zone temperature control applications.

Abstract: A microprocessor (10) and corresponding system (300) is disclosed in which prefetch of instruction or data from higher level memory (11; 307; 305) may be performed in combination with a fetch from a lower level cache (16). A branch target buffer (56) has a plurality of entries (63) associated with branching instructions; in addition to the tag field (TAG) and target field (TARGET), each entry (63) includes prefetch fields (PF0 ADDR; PF1 ADDR) containing the addresses of memory prefetches that are to be performed in combination with the fetch of the branch target address. Graduation queue and tag check circuitry (27) is provided to update the contents of the prefetch fields (PF0 ADDR; PF1 ADDR) by interrogating instructions that are executed following the associated branching instruction to detect instructions that involve cache misses, in particular the target of the next later branching instruction.

Abstract: A method of controlling contrast in LCDs using dynamic LCD biasing includes the step of identifying an expected bias function as a function of LCD material, LCD operating voltage, and LCD duty cycle. The expected bias function is then approximated to obtain a linear description of the expected bias function. A voltage is generated that follows the linear description of the expected bias function. The step of generating the voltage results in dynamic LCD biasing.

Abstract: An integrated circuit includes a voltage supply internal to the integrated circuit and circuitry for sensing the voltage level of the internal voltage supply, the circuitry responsive to produce a flag signal, VPUEN, that is in a first logical state when the voltage level is below the desired level and in a second logical state when the voltage level is above the desired level. The integrated circuit also includes a buffer driver 406 having an input terminal and an output terminal, the input terminal being coupled to the circuitry for sensing the voltage level of the internal voltage supply. The operation of the circuit is such that the output terminal 400 of the buffer driver is in a high-impedance state when the flag signal is in the first logical state, and is responsive to data signals on the input terminal to produce corresponding output signals at the output terminal when the flag signal is in the second logical state.

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc.. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.