Abstract: A programmable fast comparison circuit for determining whether the result of a logic operation on two operands is the same as a specified number in advance of the completion of the actual operation includes four fast compare units coupled to each operand signal pairs of the same degree of significance for identifying possible result signal pairs of the same degree of significance. Each fast compare circuit generates a positive signal when a result signal pair is possible based on the corresponding operand bit signal pairs. Control signals determined by the specified number signal pair of the same degree of significance is used to activate one of the four fast compare circuits with the corresponding result signal pair. When the fast compare circuit activated by the control signals is a circuit generating a positive signal, the positive signal is transmitted to a combinatorial circuit.

Abstract: An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

Abstract: A sequence controller (18) for controlling load/reset sequences for a spatial light modulator (15). The sequence controller has a program memory (41) for storing load instructions and reset instructions. A load control processor (42) executes load instructions. A reset control processor (43) executes reset instructions. The two processors (42, 43) operate independently except for synchronization.

Abstract: A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal.

Abstract: A method and apparatus for interfacing a serial data signal having an associated data clock signal to a circuit, which is clocked at a slightly higher local clock frequency, employs a D-type flip-flop to sample the data clock signal at the local clock frequency. Another D-type flip-flop stores the sample previous to that stored by the first flip-flop and on the basis of these two stored samples a decision is made as to which clock pulses of the local clock should be passed by a gate to form a modified clock signal. This modified clock signal is used to clock a third flip-flop which reads in the bits of the data signal. The modified clock signal can then be used to clock the data through a shift register so that it can be converted to a parallel format.

Abstract: A mount (10) for an integrated circuit, which permits the integrated circuit to be accurately positioned relative to other system components. The mount (10) rests on a base (200) that is part of some other system component and that has two mounting posts (210). The main body of the mount (10) is a frame (110) that holds the integrated circuit and has post apertures (120) that receive the mounting posts (210). The frame (110) has interior channels (170) that extend from the post aperture and that contain plunger/spring pairs (150, 160). A screw (181) pushed against a wedge-shaped end (152) of a plunger (150) causes the plunger (150) to push against a mounting post (210), causing the mount (10) to move relative to the base (200). The plunger/spring pairs (150, 160) provide translational and rotational adjustments. A tripod arrangement of set screws (181) provides adjustment of tilt and height. An inner frame (53) can be added to provide for electrical connections.

Abstract: A gain stage circuit includes a first transistor Q.sub.3 having a control node coupled to a bias node V.sub.B1 ; a second transistor Q.sub.2 having a control node coupled to the bias node V.sub.B1 ; a third transistor Q.sub.1 coupled in series with the second transistor Q.sub.2 and having a control node coupled to an input node V.sub.IN ; a fourth transistor Q.sub.5 matched to the second transistor Q.sub.2 and having a control node coupled to the bias node V.sub.B1 ; a current subtracting circuit 22 coupled to the second and fourth transistors Q.sub.2 and Q.sub.5 ; and a quiet current generator 20 coupled to the current subtracting circuit 22, the current subtracting circuit 22 subtracts a current in the fourth transistor Q.sub.5 from a quiet current in the quiet current generator 20.

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A dry etch process for stripping LOCOS nitride masks (302) with fluorine based removal of oxynitride (312) followed by fluorine plus chlorine based removal of nitride (302) and any silicon buffer layer (303) without removal of pad oxide (304).

Abstract: Decoding apparatus for decoding received adaptive differential pulse code modulation data signals which includes unit for quickly detecting errors in the data values in the form of unallocated values or values which are unlikely to occur. The apparatus is intended for use in cordless telephones to eliminate extraneous and disturbing sound signals which can be generated by the decoding apparatus when the signals received by the telephone become weak and are misread before a cyclic redundancy check circuit detects the error.

Abstract: A scanned antenna array and the ferrite scanning source controlling the array which includes a ferrite scanning line source (21) comprising a ferrite element (23) having an RF input (25), a current source (31) extending through the ferrite element and a plurality of RF outputs (27) spaced apart along the ferrite element and an antenna element (33) coupled to each of the RF outputs. Each of the RF outputs is equally spaced apart from adjacent RF outputs. The ferrite element has an input end portion and an output end portion and an axis therebetween, the RF outputs being disposed along the axis. The ferrite element comprises a pair of ferrite toroids (43, 45) spaced apart by a layer of dielectric material (47), the RF outputs (49) being disposed in the dielectric material.

Abstract: A test access port for an integrated circuit (or circuits) having a test register and a controller is provided. The controller enables the testability functions that have been selected by the test register. The test register performs the select function and the controller performs the enable function. An integrated circuit, having operation circuitry having nodes and external terminals for input and output of signals during normal operation, a test controller connected to at least a first one of said external terminals for receiving signals and for providing output signals during a test operation, and a test register for containing signals representative of selected tests to be performed connected to said test controller and at least a second one of said external terminals and responsive to said output signals of said test controller for enabling selected tests is provided.

Abstract: A method for operating a scan-line video processor that allows for vertical scaling with no additional memory in a display system and extracts more SVP instructions in vertical down scaling applications. The input and output sync periods of the SVP (16) are controlled such that the SVP (16) produces output lines of interpolated data that is a vertical scaling factor of the input lines. The data is then sent to a memory (24) to correct for centering and time base changes in the interpolated data. Finally, the data is sent to a display device, such as a CRT or a spatial light modulator.

Abstract: A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.

Abstract: A submicron filter assembly (24) is added to an exhaust gas controlled destruction and oxidation unit (10). Controlled destruction and oxidation unit (10) treats exhaust gas from at least one semiconductor wafer fabricating reactor. The submicron filter (24) filters submicron particles out of the treated exhaust gas to prevent visible plumes from forming in wafer fab exhaust systems (stacks). The controlled destruction and oxidation unit (10) and submicron filter assembly (24) are ideally suited for use at the point of generation of the exhaust gases. In one embodiment of the invention, the submicron filter assembly comprises an electrostatic filter (26). The electrostatic filter (26) includes a positively charged first grid (28) and a grounded second grid (30). The second grid may include a mist screen for removing particulate build-up. In another embodiment of the invention, the submicron filter assembly (36) comprises a mist eliminator (38) and a HEPA filter (40).

Abstract: A point-to-multipoint or two-way communications system is provided by a nodal transmitter located in a node with a plurality of nodal antennas radiating different polarization signals about the node. The system includes subscriber stations with directional antennas adapted to receive signals radiated from the nodal transmitter. The system may additionally include capability for transmitting and radiating subscriber signals to the nodal transmitter location for two-way communications.

Abstract: A semiconductor memory device includes an array of storage cells, each cell having a transfer transistor with a gate electrode. A separate wordline 32 interconnects the gate electrodes of each row of the storage cells. A first conductive layer includes stripes 38, each stripe overlying a different row of the storage cells and connecting to the wordline and the gate electrodes of the storage cells of a different odd numbered row of the storage cells. An insulator surrounds the stripes of the first conductive layer. A second conductive layer, separated from the stripes of the first conductive layer by the insulator, includes stripes 39, each stripe of the second conductive layer overlying a different even numbered row of storage cells and connecting to the wordline and the gate electrodes of the different even numbered row of storage cells.

Abstract: A novel micro-electro-mechanical (MEMS) RF switch having a cavity (32) in a substrate (28) which creates a spacing between a conductive membrane (34) and a bottom electrode (38). The invention eliminates the need for the dielectric posts found in prior art MEMS RF switches, includes a flexure structure (36) in the membrane (34) which will reduce the required pull down voltage for the membrane, and reduces the stress and fatigue in the membrane due to switch activation.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239).