Abstract: A random access memory (RAM) having a bipolar reduction in array operating voltage is disclosed. In a preferred embodiment, a clamping transfer gate circuit (414) couple pairs of bit lines (BL and /BL) to pairs of sense nodes (410 and 412). The clamping transfer gate circuit (414) includes an n-channel MOS transistor (N401 and N402) in series with a p-channel MOS transistor (P401 and P402) coupling a bit line (BL or /BL) to a sense node (410 or 412). The gates of the n-channel transistors (N401 and N402) are driven by the high power supply voltage (VDD), and the gates of the p-channel transistors (P401 and P402) are driven by the low power supply voltage (VSS). A sense amplifier circuit (418) drives the sense node pair (410 and 412) to opposite power supply voltages (VDD and VSS). The n-channel transistors (N401 and N402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a maximum level of VDD-Vtn, where Vtn is the n-channel transistor threshold voltage.

Abstract: A static random access memory array (200) with power supplies and an array biasing scheme is disclosed. A power supply (202) has an output voltage that is applied to the bitlines (40). The output voltage pre-charges the bitlines (40) to read from the memory cells (10). An array power supply (204) has an array voltage that is applied to the memory cells. The array voltage is higher than the output voltage. The array power supply (204) is drived by boosting the output voltage of the power supply (202).

Abstract: An embodiment of the instant invention is a method of forming a dielectric layer, the method comprising the steps of: providing a semiconductor substrate (substrate 12), the substrate having a surface; forming an oxygen-containing layer (layer 14) on the semiconductor substrate; and subjecting the oxygen-containing layer to a nitrogen containing plasma (plasma 16) so that the nitrogen is either incorporated into the oxygen-containing layer (see regions 18, 19, and 20) or forms a nitride layer at the surface of the substrate (region 22). Using this embodiment of the instant invention, the dielectric layer can be substantially free of hydrogen. Preferably, the oxygen-containing layer is an SiO.sub.2 layer or it is comprised of oxygen and nitrogen (preferably an oxynitride layer). The plasma is, preferably, a high-density plasma. Preferably, a source of nitrogen is introduced to the plasma to form the nitrogen containing plasma. The source of nitrogen is preferably comprised of a material consisting of: N.sub.

Abstract: An architecture for a high-capacity high-speed semiconductor memory device is disclosed. The semiconductor memory device includes memory cell arrays (406) having local word lines and bit lines. The memory cell arrays (406) are further arranged into array groups (402a-402d and 404a-404d). The local word lines (410a-410d) of the memory cell arrays of the same group are commonly connected to global word lines (408). The array groups (402a-402d and 404a-404d) provide data access paths to their respective memory cells by sets of input/output (I/O) lines (416a-416d and 420a-420d). The I/O line sets (416a-416d and 420a-420d) are coupled to data amplifiers by interarray multiplexers (MUXs) (422a-422d). The interarray MUXs (422a-422d) enable defective global word lines of one array group to be replaced by redundant global word lines of an adjacent array group.

Abstract: A data converter (20) comprising an input (I.sub.0 '-I.sub.3 ') for receiving a digital word and an output (V.sub.OUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0'-BL3') formed with an alignment in a first dimension and a plurality of word lines formed (WL0'-WL3') with an alignment in a second dimension different than the first dimension. Still further, the data converter comprises a string (12') comprising a plurality of series connected resistive elements (R10-R24) and a plurality of voltage taps (T10-T25), where at least a majority of the plurality of series connected resistive elements are formed with an alignment in the second dimension. Lastly, the data converter comprises a plurality of switching transistors (ST10-ST25) coupled between the plurality of voltage taps and the output.

Abstract: A liquid cooled light pipe is disclosed which allows effective pyrometric temperature measurements using a remote detector. Temperature of the light pipe assembly is controlled and maintained at an approximately constant value in order to establish good long-term temperature measurement accuracy. The temperature-controlled light pipe assembly of this invention can be used for multi-point temperature measurements of a heated body with good spatial resolution for real-time multi-zone temperature control applications.

Abstract: A semiconductor memory device sensing circuit (400) is disclosed. The circuit includes a number of sense amplifiers (402), each of which is coupled to a first supply node (414) by a first driver device (P404-0 to P404-n), and to a second supply node (420) by a second driver device (N404-0 to N404-n). An increased driving current capability is provided by a number of first boost capacitors (C400) coupled between the first supply node (414) and an intermediate voltage (Vplate), and a number of second boost capacitors (C402) coupled between the second supply node (420) and the intermediate voltage (Vplate).

Abstract: A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal.

Abstract: A semiconductor memory emphasizing manipulated clocking and buffering to increase operating speeds.

Abstract: A submicron filter assembly (24) is added to an exhaust gas controlled destruction and oxidation unit (10). Controlled destruction and oxidation unit (10) treats exhaust gas from at least one semiconductor wafer fabricating reactor. The submicron filter (24) filters submicron particles out of the treated exhaust gas to prevent visible plumes from forming in wafer fab exhaust systems (stacks). The controlled destruction and oxidation unit (10) and submicron filter assembly (24) are ideally suited for use at the point of generation of the exhaust gases. In one embodiment of the invention, the submicron filter assembly comprises an electrostatic filter (26). The electrostatic filter (26) includes a positively charged first grid (28) and a grounded second grid (30). The second grid may include a mist screen for removing particulate build-up. In another embodiment of the invention, the submicron filter assembly (36) comprises a mist eliminator (38) and a HEPA filter (40).

Abstract: A redundancy circuit (300) for generating a standard column access signal (STD) and a redundant column access signal (RED) is disclosed. A modified NOR-type decoder (310) determines if an applied address is the same as a defective address. In the event the applied address is the same as the defective address, a match indication is activated. In the event the applied address is different than the defective address, a no match indication is generated. The match indication activates the RED signal and the no match indication activates the STD signal, according to the timing of a "mimic" circuit (312). The mimic circuit (312) emulates the slowest resolution of the match/no match indication by the modified NOR-type decoder (310).

Abstract: A memory cell array architecture (300) for memory cells having a 6F.sup.2 area, where F is a minimum feature size, is disclosed. The array architecture (300) includes active areas (302a-302n) arranged into even columns and odd columns. The active areas (302a-302n) each include a central portion (306) and are separated from one another within a column by column spacing structures (308). The active areas of even columns are offset from those of odd columns so that the central portion the even column active areas are aligned, in the row direction, with the column spacing structures of the odd columns. This arrangement allows bit line contacts (312a-312g) to be formed at the central portions with less restrictive alignment constraints. Two storage node contacts (316a-316t) are also formed to each active area (302a-302n). A novel lithography mask for improved creation of the storage node contacts is also disclosed.

Abstract: In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.

Abstract: A voltage regulator circuit (100), coupled between a high power supply voltage (VCC) and a lower power supply voltage (VSS), provides a regulated voltage (XDD) that is greater than the high power supply voltage (VCC). The voltage regulator circuit (100) includes a temperature compensating detect circuit (102) which activates a trigger signal when the XDD voltage exceeds a predetermined level. In response to an active trigger signal, a shunt circuit (104) couples the regulated voltage (XDD) to the high power supply voltage (VCC). The regulated voltage (XDD) is translated to the detect circuit (102) by the regulated voltage (XDD) being applied to the gate of a transistor (N112) disposed between the high power supply voltage (VCC) and a detect node (108). This arrangement allows monitoring of the regulated voltage (XDD) level without loading the regulated voltage (XDD).

Abstract: A method of forming a complementary metal-oxide-semiconductor (CMOS) integrated circuit, and the integrated circuit so formed, are disclosed. After the formation of a p-type well (4) and an n-type well (6) into which the transistors are to be formed; and gate structures (8n, 8p) overlying the surfaces of these wells (4, 6), a doped insulating layer (20) is formed overall, for example by way of chemical vapor deposition. The doped insulating layer (20) is, according to the preferred embodiment of the invention, silicon dioxide that is doped with boron. In the preferred embodiment of the invention, the portion of the doped insulating layer (20) overlying the p-type well (4) is removed, and ion implantation of n-type dopant is then performed. The remaining portion of the doped insulating layer (20) protects the n-type well (6) from the n-type ion implantation steps.

Abstract: A stacked sense-amp cache memory system and method is provided. The stacked sense-amp cache memory system (10) may comprise a memory cell array (22) coupled to a cache system (30). The memory cell array (22) stores and retrieves a data signal. Recently retrieved data signals are stored in the cache system (30). A column select system (32) is coupled to the cache system (30). A logic subsystem (12) controls the column select system (32) such that the column select system (32) directs the data signal from the memory cell array (22) to a sense-amp system (34) or directs a stored data output signal from the cache system (30) to a switching system (36). The sense-amp system (34) senses and amplifies the data signal and produces an amplified data output signal. The switching system (36) is coupled to the sense-amp system (34) and the cache system (30) and operates to select between the amplified data output signal from the sense-amp system (34) and the stored data output signal from the cache system (30).

Abstract: A TiN.sub.x layer is formed by disposing a substrate (18) in a chamber (12). A first reactant gas (40) comprising Ti, a second reactant gas (42) and a third reactant gas (44) comprising N are introduced into the chamber (12). By controlling the ratio of the first, second and third reactant gasses (40, 42, 44), TiN.sub.x is deposited onto a surface (28) of the substrate (18), where x is between zero and one.

Abstract: A synchronous dynamic random access memory (SDRAM) improves memory access time by incorporating into the column address path a bidirectional column factor counter.

Abstract: A memory circuit is designed with a memory array (113, 115, 117, 119) having a plurality of banks. Each bank is addressable in response to a bank address signal (102), and each bank arranged in rows and columns of memory cells. Each of plural data leads (122) corresponds to a bank. Each data lead is selectively connected to a column of memory cells by a respective select transistor. A first decode circuit (501) has at least one input and one output terminal. The output terminal (525) is coupled to a control gate of at least one of the select transistors. Each of a plurality of second decode circuits (231) corresponds to a respective bank. Each second decode circuit has a memory element (423, 425, 428)), a plurality of input terminals and at least one output terminal. One second decode circuit input terminal (227) is coupled to receive a first address signal. Another second decode circuit input terminal (229) is coupled to receive the bank address signal.

Abstract: A method and apparatus for testing a semiconductor serial access memory (30) device through a main memory (20) includes a semiconductor memory comprising a main memory (20) and a serial access memory (30). A test data (48) is generated and an expected test data (50) that is equivalent to the test data (48) is also generated. The test data (48) is stored in the main memory and sent to the serial access memory (30). The test data (48) in the serial access memory is then sent back to the main memory (20) and stored in the main memory (20). The test data (48) is then read from the main memory (20). Then, the test data (48) read from the main memory is compared with the expected test data (50), producing an output having a first state if the test data (48) read from the main memory (20) is similar to the expected test data (50) or a second state if the test data (48) read from the main memory (20) is different than the expected test data (50).