Abstract: A system for wireless communication between a base station 30 and one or more remote stations 32 and 34 wherein the beam pattern of the receiving antenna 50-52 can be adaptively formed to track a desired signal. A series of weights is applied, one to each output of the elements of the receiving antenna and the weighted output summed to form the antenna output. The weights are adaptively modified so as to focus the beam in the direction of one of many signals which may be present in the data received by the antenna. A least-square-error process is used to identify if the signal beamed on is the desired signal. If such is not the case, the weights are modified to null out the earlier signal and to focus the pattern on another signal.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: A test enable control for a built-in self-test of a memory device is provided. In one embodiment of the present invention, a test enabling system is provided. The test enabling system comprises an enable test circuit (62), a plurality of test algorithms stored in a read only memory (72) and a program counter (66) operable to control the execution of the test algorithm. The first instruction of each test is a jump test enable instruction (130) comprising a jump test instruction and an address in the read only memory (72) corresponding to the next test algorithm. The enable test circuit (62) is operable to signal to the program counter (66) if a particular test algorithm is enabled.

Abstract: Bank selectable Y-decoder circuit (24) generates a plurality of Y-select signals (60, 62, 64, 66) for addressing columns of a plurality of memory banks (12, 14) in a memory array (10) and includes a high-order column factors decode circuit (34) for receiving a plurality of column factor signals. A first low-order column factor circuit (30) generates a first set of Y-select signals (60, 62) for addressing at least one column of a first set of memory banks (12). A second low-order column factors circuit (32) generates a second set of Y-select signals (64, 66) for addressing at least one column of a second set of memory banks (14). The result is a Y-decoder circuit (24) that consumes less silicon die area, without a reduction in circuit performance.

Abstract: Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n, 32.sub.0 -32.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus.

Abstract: A digital computing system (30). The digital computing system includes a memory (36) and a memory controller (34). The memory comprises at least one memory bank (B0), and that bank comprises a plurality of rows (R.sub.0 -R.sub.N) and a plurality of columns (C.sub.0 -C.sub.N). The memory controller circuit is coupled to control the memory, and comprises a first bus (38) for providing an address to the memory, and three additional buses (38, 40). A first of these additional buses provides a row address strobe signal (RAS*) to the memory, where assertion of the row address strobe signal represents an indication that an address on the bus is a valid row address directed to one of the plurality of rows. A second of these additional buses provides a column address strobe signal (CAS*) to the memory, where assertion of the column address strobe signal represents an indication that an address on the bus is a valid column address directed to at least one of the plurality of columns.

Abstract: A modem that operates selectively in the voice-band frequency band and at higher frequency bands is provided. This modem supports multiple line codes, like DMT and CAP.The modem uses a Digital Signal Processor (DSP), so that different existing ADSL line codes, such as Discrete MultiTone (DMT) and Carrierless AM/PM (CAP), can be implemented on the same hardware platform. The modem negotiates in real-time, for a desired line transmission rate to accommodate line condition and service-cost requirement.The line code and rate negotiation process may be implemented at the beginning of each communication session through the exchange of tones between the modems. A four-step MDSL modem initialization process is provided for line code and rate compatibility.

Abstract: A circuit is designed with a memory array (102) having a plurality of memory cells arranged in rows and columns (204, 206, 210, 212). The memory array has a plurality of bit line pairs (202, 208, 282, 284) with each bit line pair connected to a respective column of memory cells and a bit line reference terminal (254). A control circuit (700) produces a control signal, the control signal having a first voltage for a first time, a second voltage for a second time and a third voltage for a third time. A precharge circuit (350, 352) connects at least one bit line pair to the bit line reference terminal, responsive to the first voltage for the first time and the second voltage for the second time. The precharge circuit disconnects the at least one bit line pair from the bit line reference terminal, responsive to the third voltage for the third time.

Abstract: A short disturb test algorithm for built-in self-test is provided. The short disturb test (108) initially writes a background pattern to all cells in a memory array (24). After verifying the background pattern was written, the opposite of the background pattern is written to a single row of the memory array for a fixed time. After that fixed time has elapsed, the original background pattern is written to the row. The memory array is then refreshed and the next row is written to. After all rows have been written to, the memory array (24) is checked for failures.

Abstract: A differential input buffer (14) and method of construction are provided. The differential input buffer (14) includes a differential amplifier (54, 56, 50, 52, 62, 64) connected to receive an input signal (IN). A local reference voltage generator (68, 70, 72) is connected to the differential amplifier (54, 56, 50, 52, 62, 64) and is connected to receive an external voltage reference (BLR) and to provide a local reference voltage (VREF) to the differential amplifier (54, 56, 50, 52, 62, 64). The local reference generator (68, 70, 72) is adjustable during construction to produce a desired level for the local reference voltage (VREF). The differential input buffer (14) also includes a hysteresis element (66, 74) that is connected to provide feedback to the differential amplifier (54, 56, 50, 52, 62, 64) and includes a buffer stage (76, 78, 80, 82, 84, 86) that is connected to receive an output of the differential amplifier (54, 56, 50, 52, 62, 64) and to drive an output signal (OUT).

Abstract: A data processing system includes a data processor and a random access memory arranged with plural memory planes. Each memory plane includes N memory arrays; N serial registers, each serial register coupled to a memory array; N block write control circuits; a row address decoder; and a column address decoder arranged for both block decoding and individual column decoding. An address bus and a data bus connect the data processor with all of the memory arrays. Random access for writing data into the N memory arrays may be by individual bits or by blocks of bits. The plural memory planes, the address bus, and the data bus are all fabricated on a single semiconductor substrate. A Z-buffer memory with plural Z-buffer planes may also be included. Each Z-buffer plane includes N Z-buffer arrays; N Z-buffer block write control circuits; a Z-buffer row address decoder; and a Z-buffer column address decoder arranged for both block decoding and individual column decoding.

Abstract: An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority interrupt, a RESET. The user can set the field to enable a subsequent NMI but cannot himself clear the NMI. This strategy prevents an NMI from interrupting a RESET service routine.

Abstract: The cathode of the charging capacitor (31) of the present invention is coupled to a switch (36) that is able to apply one of several voltage levels to the cathode depending on the testing or use condition of the semiconductor memory array (10). The switch switches between the voltage levels at the cathode to avoid overstressing the charging capacitor (31) during testing of the semiconductor memory array (10).

Abstract: An input protection device is presented having a depletion controlled isolation stage. In one embodiment of the invention, a depletion controlled isolation resistor is formed between adjacent N+ diffused regions by N-well diffusion. One N+ diffused region electrically contacts an input bond pad and a primary protective device. The other N+ diffused region electrically contacts a second protective device and the internal circuit it is to protect. The depletion controlled isolation resistor limits the amount of current passing through the resistor to a safe level during an over-voltage condition. In another embodiment of the invention, a depletion controlled isolation stage includes a silicon controlled rectifier (SCR) as the primary protective device in combination with the depletion controlled isolation resistor.

Abstract: The low power data line and method may comprise a line (30, 102) connecting a plurality of devices (60, 104) to an output (32, 104). The devices (60, 104) may be independently accessed to provide data to the output (32) along the line (30, 102). A switch (40, 120) may be disposed in the line (30, 102) to selectively disconnect a segment (52, 132) of the line (30, 102) connected to at least one of the devices (60, 104) from the output (32).

Abstract: A method for etching a semiconductor device (10) having BARC layer (22) and nitride layer (20) includes etching BARC layer (22) until reaching a first set point in the fabrication reaction chamber and then etching nitride layer (20) in-situ the fabrication reaction chamber immediately following etching BARC layer (22).

Abstract: A self-aligned multiple crown storage cell structure 10 for use in a semiconductor memory device and method of formation that provide a storage capacitor with increased capacitance. A double crown storage cell structure embodiment 10 can be formed by patterning a contact via 18 into a planarized base layer that can include an insulating layer 12, an etch stop layer 14, and a hard mask layer 16, depositing a first conductive layer 20, etching the first conductive layer 20, etching the hard mask layer 16, depositing a second conductive layer 24 onto the conductive material-coated patterned via 18 and the etch stop layer 14, depositing a sacrificial (oxide) layer 26 onto the second conductive layer 24, etching the sacrificial layer 26, depositing a third conductive layer 28, and etching conductive material and the remaining sacrificial layer 26. The last several steps can be repeated to form a storage cell structure 10 with three or more crowns.

Abstract: A method and system (50) reduce the apparent time between turning on a computer (10) and making available the computer (10) processing capability. The method and system (154) include the necessary steps for and instructions and circuitry for generating a startup command for the computer. The method and system include displaying within a shortened predetermined time period an interface screen (14) that includes a plurality of interface checkpoints (24) and address data relating to application programs associated with the user interface checkpoints. The shortened predetermined time period has a duration substantially shorter than the period associated with booting (60) the associated application programs. In turning off computer (10), the method and system (50) include generating a shut down command (70) to computer (10) and storing interface screen (14) and any data files (78) that are open at the time of turning off computer (10).

Abstract: In a system (12) wherein articles are manufactured by a plurality of process steps (20, 22, & 24), a method for identifying causes of variations in performance of the manufactured articles is provided. The method includes tracking orientation data (48) for the articles during each of the process steps (20, 22, & 24) and then measuring (50) performance data for each of the articles. The method also includes preparing surface performance characteristic maps (54) for each of the articles from the performance data and ordering the surface performance characteristic maps (56) for each of the articles in accordance with the orientation data for each article at a given process step (20, 22, & 24).

Abstract: A read-only memory (ROM) embedded mask release number for a built-in self-test of a memory device is provided. A synchronous dynamic random access memory (10) comprises a conventional memory (12) and a built-in self-test arrangement (14). The built-in self-test arrangement (14) includes a read only memory (ROM) (72) which stores a plurality of algorithms. Each algorithm is comprised of a series of array access instructions (140) and program access instructions (142). The last instruction in ROM (72) is an idle instruction (120). Associated with idle instruction (120) is an identification number (132). Once stored in ROM (72), the identification number (132) can be read without the use of additional equipment.