Abstract: A sensing arrangement (100) for a dynamic random access memory (DRAM) is disclosed. The sensing arrangement (100) includes a sense amplifier bank (104) that is logically divided into a number of sense amplifier groups (106-1 to 106-2.sup.m). In a read operation, a given number of memory cells are coupled to the sense amplifier bank (104), and one sense amplifier group will provide read data while the remaining sense amplifier groups will refresh memory cell data. A timing circuit (102) receives a timing signal (EVAL) and address information (A1-Am) and in response thereto, enables the sense amplifier group that provides read data before the sense amplifier groups that refresh memory cell data. Peak current is reduced and improved sensing speed result.

Abstract: A circuit for charging or discharging a capacitive load. The circuit includes a buffer driver comprising first and second input terminals and an output terminal, and a reference voltage generator coupled to the buffer driver. The reference voltage generator includes an enablement signal terminal, first and second reference voltage terminals, and a circuit operable to provide first and second reference voltages at the first and second reference voltage terminals in response to a first signal at the enablement terminal. The reference voltage generator also provides first and second rail voltages in response to a second signal at the enablement terminal.

Abstract: A semiconductor memory device having a redundancy scheme is disclosed. A memory cell array includes a number of standard word lines sets and at least one redundant word line set. Each standard word line within a standard word line set is selected by lower address signals, and couples memory cells to a different combination of bit line than the other standard word lines within the standard word line set. In a standard mode of operation, transfer gates coupled to each bit line are enabled according to the lower address signals. Each redundant word line within a redundant word line set is selected by a defective address, and couples memory cells to a different combination of bit lines than the other redundant word lines within the redundant word line set. In a redundant mode of operation, the transfer gates are enabled according to an activated redundant word line to ensure that the proper combination of bit lines is coupled to sense amplifier circuits.

Abstract: An ESD protection circuit for dual 3V/5V supply devices. ESD protection circuit 10 comprises a switching element 12 connected between a bond pad 14 and primary protection device 16. Primary protection device 16 comprises MOS circuitry designed for 3V operation that suffers from oxide reliability problems when 5V signals are applied directly. Switching element 12 separates the primary protection device 16 from 5V signals which may appear at bond pad 14.

Abstract: This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation.

Abstract: This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.

Abstract: A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signal (*CLK) in response to the second logic state. The second clock signal has a frequency at least twice a frequency of the first clock signal. An address counter (221) is coupled to receive one of the first and second clock signals. The address counter produces a sequence of address signals corresponding to the one of the first and second clock signals. An array of memory cells is arranged to produce a sequence of data bits corresponding to the sequence of address signals. A logic circuit (235, 239, 240) is coupled to receive the sequence of data bits. The logic circuit produces a logical combination of the sequence of data bits.

Abstract: The invention provides a process for evaluating a substrate, such as a wafer of semiconductive material having a semiconductor die at least partially formed thereon, as to the condition of an overlying film, such as an overlying film of photoresist that is applied to the semiconductor die prior to metal etching and ion implantation. The condition of the film is evaluated by exposing at least a portion of the substrate to electromagnetic radiation and evaluating the wave profile of the reflected beam.In instances where it is desirable to evaluate the substrate for the presence or absence or photoresist, ultraviolet, or near ultraviolet light having a wavelength of about 240-650 nm can be used, as such wavelengths are strongly absorbed by photoresist. In contrast, areas of the substrate that are not covered by photoresist will not significantly absorb ultraviolet or near ultraviolet radiation.

Abstract: A memory configuration (20). The memory configuration comprises a plurality of memory cells (SCI1, SCI2, SCI3) arranged in a plurality of rows and columns. The memory configuration also comprises a plurality of wordlines (WL.sub.0 -WL.sub.N). Each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period. In addition, each of the plurality of memory cells comprises at least one transistor (e.g., AT3) coupled to receive a back bias. The memory configuration also comprises circuitry for providing a first back bias operable to cause only the at least one transistor in each of the memory cells in the selected row (e.g., WL.sub.

Abstract: A method for forming a semiconductor memory device storage cell structure having an increased surface area. The storage cell structure has one or more rough polysilicon surfaces formed by depositing the polysilicon under conditions that result in gas phase dominant nucleation.

Abstract: A flash electrically erasable and programmable read only memory (EEPROM) having a selective parallel sector erase capability (100) is disclosed. The flash EEPROM (100) includes a number of sectors (104-0 to 104-18), each of which receives an erase voltage (VCC) by way of a source switch circuit (112-0 to 112-18). The source switch circuits (112-0 to 112-18) are each enabled by logic values stored in corresponding tag registers (114-0 to 114-18). The logic values stored by the tag registers (114-0 to 114-18) can be established by the application of particular address values (A12 to A18). The logic values of the tag registers (114-0 to 114-18) can be simultaneously reset to the same value by the application of other address values (A9).

Abstract: A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N.sup.+ control gate (26) is formed in P-well (14) and includes punch-through implant region (26). NMOS transistor (16) and N.sup.+ control gate (26) have in common electrically isolated polysilicon gate (22, 32) for operating as a floating gate in common with NMOS transistor (16) and N.sup.+ control gate (26). N.sup.+ control gate (26) includes P-channel punch-through implant (34) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (10).

Abstract: A method of forming a suicide layer 12 is disclosed herein. In one embodiment, a refractory metal (e.g., titanium) layer 20 is formed over a silicon (e.g., polysilicon) layer 10. The silicon layer 10 and the titanium layer 20 are then heated to a first temperature so that the silicon 10 and titanium 20 react to form a titanium silicide region 12. While applying an external force to warp the device, the titanium silicide region 12 is heated to a second temperature. This second temperature is higher than the first temperature. In one embodiment, this two-step heating process helps facilitate the transition from C49 phase TiSi.sub.2 to C54 phase TiSi.sub.2.

Abstract: A balanced sensing scheme (300) for a "flash" electrically programmable and erasable read only memory (EEPROM) is disclosed. In a read operation, an upper memory cell bank (302a or 302b) and a corresponding lower memory cell bank (302c or 302d) are coupled to a sense amplifier bank (306). One of the memory cell banks provides data while the other functions as a balanced load. In the event the memory cell bank that is to function as the balanced load is in the process of being erased, an alternate memory cell bank is coupled to the sense amplifier bank (306) to provide an equivalent balanced load.

Abstract: A leakage tolerant sense circuit for use in an electrically programmable and erasable read only memory (EEPROM) is disclosed. In a reference portion of a sense cycle, the leakage tolerant sense amplifier utilizes the sum of a reference current and any leakage current to establish a reference voltage. In the subsequent sense portion of the sense cycle, the leakage tolerant sense amplifier utilizes the sum of a memory cell current and any leakage current to establish a read voltage. The read voltage is compared with the reference voltage to determine the logic stored within the memory cell.

Abstract: A memory circuit (10) provides reduced array sense amplifier circuitry (20, 22) for a memory cell array (24, 26, 28, 30), which has a plurality of memory cells (340) for electrically storing data. A plurality of bitlines (260) are associated with a memory cell array (26) for carrying data to and from the memory cells therein. At least one sense amplifier circuit (16) includes circuitry (332, 334) for addressing selected memory cells via column select lines, and for communicating with an external source of address signals. A local sense amplifier circuit (20, 22) includes circuitry (262, 266) for communicating with the sense amplifier circuit through the selected bitlines. The local sense amplifier circuit also includes circuitry (234, 238) for communicating with other bitlines (232, 236) for addressing other memory cells (28), and further for transmitting data to and from the other memory cells along the selected bitlines, in cooperation with the sense amplifier (16).

Abstract: Circuits for applying a programming voltage and erase voltage to memory cells in a nonvolatile memory device are disclosed. The reverse breakdown of p-n junctions within the memory cells is prevented by providing a clamping p-n junction in the path used to apply the program or erase voltage to the memory cells. The clamping p-n junction will breakdown before the p-n junctions within the memory cells, protecting the memory cells from the adverse effects of a reverse breakdown condition.

Abstract: Traditionally, hydrofluoric acid (HF) or buffered bydrofluoric acid (NH.sub.4 F) is mixed with water to form a etching solution for cleaning silicon dioxide from semiconductor wafer surfaces. An etching solution formed by mixing ammonium hydrogen bifluoride ((NH.sub.4)HF.sub.2) with water provides a benign alternative for cleaning silicon dioxide.

Abstract: A data output system (100) is disclosed. The data output system (100) includes a number of data output paths (102a-102h) which provide data output signals (DQ0-DQ7) to a data bus. An invert data path 104 provides an invert data signal (INVOUT) that indicates when the data output signals (DQ0-DQ7) have been inverted to reduce the number of transitions on the data bus. A voter circuit (106) determines when data output signal inversion occurs, and includes a local data comparator (132a-132h) associated with each data output path (102a-102h). Each data comparator (132a-132h) compares a current data output signal (D0-D7) with a next data output signal (DN0-DN7), and in response thereto, generates a differential on a pair of data compare lines (138 and 140). The differential on the data compare lines (138 and 140) is amplified by a differential amplifier (136) to generate the invert output signal (INVN) for the following data output cycle.

Abstract: A miniaturized integrated sensor (50) useful for indicating the presence of a sample analyte is disclosed. The sensor (50) has a platform (52) with an upper surface (53) and a detector (62), light source (60), waveguide (58), and reflective fixtures (60,62) embedded in the platform (52). The light source (60) is preferably a light emitting diode and sits in a cup-shaped dimple (68) that directs light from the light source (60) toward one of the reflective fixtures (64) to uniformly distribute light across the waveguide (58). The waveguide (58) is coupled to an upper surface (53) of the sensor platform (52) and is coated with a thin film of indicator chemistry (70) which interacts with the sample analyte to produce optic signal changes that are measurable by the detector (62). A lead frame (51) in the platform (52) has pins (54, 55, 56) which provide the interface to the outside world.