Abstract: The present invention relates to a mains-power electrical connector. The connector includes a core defining passages for receiving respective cables, and apertures for receiving fasteners to fasten the cables within the passages. Windows terminate the passages. A light penetrable cover is provided for covering the core and the windows. The fasteners may be in the form of shear bolts.

Abstract: Systems, apparatuses, methods, and computer program products for performing silicon debugging and isolating faults in integrated circuits are disclosed. Some embodiments comprise a simulator to simulate operation of one or more portions of a circuit in order to identify elements of the circuit which are related to a fault, a circuit pruner to separate the related elements from other elements of the circuit and correlate the related elements to a physical layout of the elements, and a probe tool to locate one or more of the related elements which cause or contribute to the fault. Alternative embodiments may comprise computer programs for simulating operation of a circuit to determine related elements of a fault, correlating the related elements to a physical layout or arrangement of the elements in the circuit, and testing the related elements via the physical layout to determine which elements contribute to the fault.

Abstract: Embodiments include systems and methods for allowing a host CPU to sleep while service presence packets and responses to search requests are sent by an alternate processor. While the CPU is in a low power state, the alternate processor monitors the network for incoming request packets. Also, while the CPU is asleep, the alternate processor periodically may transmit presence packets, announcing the presence of a service available from the host system of the CPU. In one embodiment, the alternate processor is a low power processor. If a search request is received when the CPU is in a low power state, the alternate processor responds to the search request according to whether the PC provides that service. If a service request is received, then the ME wakes the CPU of the PC to provide the requested service. In the wireless case, when the CPU is asleep, portions of the wireless upper MAC are implemented by the ME. When the CPU is awake the wireless upper MAC is implemented in the CPU.

Abstract: Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data when the phase between the incoming data and the receiver clock varies relatively slowly. Embodiments comprise a fast tracking loop performs to track the data when the phase between the incoming data and the receiver clock varies rapidly. The fine tracking loop adjusts the phase of a receiver clock to track the data eye of the data. The fast tracking loop over-samples the data and then chooses the sample that best represents the data. In some embodiments, the data recovery circuit can switch between receiving data from the fine tracking loop and receiving data from the fast tracking loop.

Abstract: A method for encoding data is disclosed. The method can include receiving a first bit segment (K?1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K?1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.

Abstract: Apparatuses, systems, and methods to monitor core performance and integrated circuit chip temperatures in order to alternatively partition cores and core resources are disclosed. Embodiments generally comprise integrated circuit processors in chips that contain multiple cores or processing elements. In many system and apparatus embodiments, a module monitors either the throughput or performance of one or more of the cores. In such embodiments, another module, a core allocation module, partitions or allocates cores in different arrangements of partitions to improve performance. Additionally, in some embodiments, a temperature monitoring module monitors one or more temperatures of the chip containing the cores, wherein the temperature measurements may affect the core allocations. In some embodiments, once an allocation for the cores is selected, the specifics of the cores to be placed in different partitions may be stored and later retrieved when triggered by events allowing for the reallocation of the cores.

Abstract: A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.

Abstract: Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.

Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

Abstract: Systems, methods and media for verifying the existence of a licensed software installation at the time of an update to the software are disclosed. In one embodiment, a package of files for the update is encrypted with a copy of a key file that is contained in the original installation. The encrypted package of files is stored at a remote location that is accessible by way of a website. When a user seeks to download an update, the user must provide a copy of the key file used to encrypt the data. The user-provided key file is then used to decrypt the encrypted package.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: In one embodiment a micro-electro mechanical system is disclosed. A MEMS structure can include a frame, a movable structure and a set of structural beams to suspend the movable structure from the frame. The system can also include a set of conductor routing beams. The conductor routing beams can provide a conductive path from the frame to the movable structure. The set of structural beams can have a spring rate that is more than ten times the spring rate of the set of conductor routing beams. Accordingly, multiple routing beams can be utilized to support multiple conductors without significantly affecting the mechanical movement or dynamic properties of the movable structure.

Abstract: In some embodiments a method is disclosed that includes creating a network connection status between a host device and a peripheral network device, determining characteristics of the peripheral device such as receive capacity or a quality of service classification for the transmission and flow control for performing control and data transfers. A transfer is initiated when a uniform serial bus request block (URB) is generated by a host application. The URB can have parameters that can be utilized to generate a transaction over a wireless network providing Quality of Service (QoS) guarantees. Other embodiments are also disclosed.

Abstract: Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: Embodiments include hardware and/or software for manufacturing a removable plate having a medium, to be integral to a casing for a processor-based device. Integrating the removable plate in or on the casing facilitates access to the medium and the data stored on the medium by providing storage in a location that is convenient and local to the processor-based device. The removable plate may include a first surface designed to cover a portion of the processor-based device and a second surface to be covered by the first surface when integrated with the casing, to provide access to the medium. The removable plate may also include any other types of media that can communicatively couple with the processor-based device directly, or indirectly through, e.g., a computer network.

Abstract: Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments an apparatus that has a receiver and a wear leveling module. The receiver may receive low-level write requests to update direct-mapped values of nonvolatile memory. The wear leveling module may determine physical locations of the nonvolatile memory that correspond to logical locations of the write requests. Alternative embodiments may comprise systems or apparatuses that include one or more various types of additional modules, such as low-level driver modules, error correction code modules, queue modules, bad block management modules, and flash translation layer modules. Other embodiments comprise computer program products that receive a direct-mapped low-level write request, determine a physical write location of nonvolatile memory that corresponds to a logical write location of the low-level write request.

Abstract: A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

Abstract: Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.

Abstract: Methods and arrangements to provide computer security are contemplated. Embodiments include transformations, code, state machines or other logic to provide computer security by receiving over a secure network connection a message to signal physical presence to a trusted platform module (TPM) and by signaling physical presence to the TPM in response to receiving the message. Some embodiments may involve sending the message over a secure network connection. In some embodiments, the receiving may be performed by a platform system management module. In many further embodiments, the signaling may include sending a signal over a secure general purpose input/output (GPIO) line or other hardware signaling mechanism. Other further embodiments may include sending a message pursuant to the intelligent platform management interface (IPMI) or other remote management protocol. In other embodiments, the receiving may be performed by a network stack of a basic input/output system. Other embodiments are described and claimed.

Abstract: Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session preferences including a selection of one or more assertion schemas for use in generating the assertions, where the selected assertion schema each have one or more design attributes. The embodiment may also include parsing the design to determine locations in the design for the assertions based on the design architecture, structure, and hierarchy and generating the assertions based on at least the session preferences, the determined locations for the assertions, and the design attributes associated with the selected assertion schema.