Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: A path controller 10 creates a logical tree LT having a plurality of member trees MT1 and MT2 within a routing table 52 at the time of initial setting. Direct tables DT1 and DT2 for the member trees MT1 and MT2 have the same DT entries (root). Unlike a conventional tree in which a single tree is constructed for the same root, since the present invention is such that the plurality of member trees are constructed for the same root, the number of nodes N passed through before reaching leaves L is reduced. At the time of path search, a plurality of search engines SE1 and SE2 search the member trees MT1 and MT2, respectively.

Abstract: Embodiments may comprise logic such as hardware and/or code within a heterogeneous multi-core processor or the like to coordinate reading from and writing to buffers substantially simultaneously. Many embodiments include multi-buffering logic for implementing a procedure for a processing unit of a specialized processing element. The multi-buffering logic may instruct a direct memory access controller of the specialized processing element to read data from some memory location and store the data in a first buffer. The specialized processing element can then process data in the second buffer and, thereafter, the multi-buffering logic can block read access to the first buffer until the direct memory access controller indicates that the read from the memory location is complete. In such embodiments, the multi-buffering logic may then instruct the direct memory access controller to write the processed data to other memory.

Abstract: Methods and systems to dynamically configure computing apparatuses, such as desktop computers and portable computing devices, are disclosed. Embodiments generally comprise configuration systems that communicate with the computing apparatuses, retrieve hardware and/or software information from the apparatuses, and use the information to configure and/or load software onto the apparatuses. The computing apparatuses being configured may comprise desktop computers, computer workstations, or servers, as well as handheld and/or portable computing devices such as notebook or palm-held computers, cellular telephones, and portable media players. In many embodiments, the configuring systems compare information pertaining to installed hardware and software of the computing device, compare the information to software compatibility databases, select software and other configuration information based upon the comparison, and configure the computing apparatuses with the selected software and other configuration information.

Abstract: Embodiments include systems and methods for scheduling transmissions of information in a wireless network. Embodiments comprise determining a service interval that is a multiple of a service interval granularity period, the multiple depending upon a type of information to be transmitted during the service interval.

Abstract: Systems; articles of manufacture, and methods to coat vehicular plastics with an epoxy are disclosed. Embodiments of the invention provide an extremely durable epoxy coating on various plastic parts of a vehicle. One embodiment includes a system that may be used to remove damaged plastic and any existing hard coat material, such as silicone, from the surface of a vehicular plastic. Such embodiments may also include the epoxy coating and tools necessary for applying the epoxy. Another embodiment discloses a process for preparing and sealing a vehicular plastic with an epoxy coating.

Abstract: Systems, methods and media for migration of a guest from one server to another are disclosed. In one embodiment, a first server, while hosting the guest, receives a signal from the second server that the migration is to occur. The first server presents the memory used by the guest as a virtual disk. The second server accesses this disk and copies its contents to the second server over the storage area network. The first server suspends operation of the guest, and after the memory of the guest is copied to the second server, the second server resumes operation of the guest.

Abstract: A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address conversions in the NAND based memory, where the address conversions can relate logical addresses to a physical address. At least one validity flag can be assigned to the address conversions. The processor can perform a direct read of the operating system instructions from the NAND based memory in response to a first setting of a validity flag and the processor can perform an indirect read of the operating system instructions by fetching an address conversion from the NAND based memory in response to a second setting of the at least one validity flag.

Abstract: Methods, systems, and media to define a portion of a circuit pattern with a source of real-time configurable imaging are disclosed. Embodiments include hardware and/or software for directing a beam through a mask onto a wafer surface to outline a circuit pattern having an undefined area, directing a second beam to the semiconductor wafer surface to define a circuit structure in the undefined area to complete the circuit pattern on the semiconductor wafer surface, and directing the second beam onto a source of real-time configurable imaging. Embodiments may also include a mask to include an undefined area incorporated into the circuit pattern to leave a critical structure of the circuit pattern undefined. Several embodiments include a photolithography system including an exposure tool, a mask, a source of real-time configurable imaging, and addressing circuitry.

Abstract: Systems for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.

Abstract: Methods, systems, and media to enhance memory leakage management by identifying a suspect allocation pattern during execution of a task, which may be indicative of memory leakage and implementing measures to protect against memory leakage based upon the suspect allocation pattern, are disclosed. More specifically, embodiments may detect a suspect allocation pattern by monitoring memory allocations and deallocations for tasks. The pattern of memory allocations and deallocations may then be analyzed to determine whether a suspect allocation pattern exists. For instance, the memory allocations and deallocations may be compared to determine whether there is an increasing net residual allocation left by the task after it has reached a quiescent runtime state. In some embodiments, a suspect allocation pattern exists if the total memory allocation for a task continues to rise after a pre-determined time period.

Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.