Abstract: A method to achieve good stepper focus and exposure over an entire wafer for a particular mask level before the start of a product run is described. This method can also be used to produce a characterization of lens field curvature (i.e., a surface of optimum focus across the lens) and to characterize lens astigmatism, defocus sensitivity, relative resolution, and other characteristics, and to check the stepper for optical column tilt. The process prevents the complexities of resist development from affecting determination of focus. The process involves forming an array of latent images in a resist and examining the scattered light from the edges of the latent images. Analysis of the scattered light quickly provides information on correct exposure and focus together with lens characteristics over the printing field.

Abstract: The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.

Abstract: The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.

Abstract: A twin tub integrated circuit and method for its formation are disclosed. A portion of the substrate is covered by photoresist while an n region is formed, illustratively, by ion implantation. Then the n region is covered with a protective material, illustratively a spin on glass or another photoresist. The previously-formed photoresist is removed and a p-type implant is performed to create an p region. When all the protective layers are removed, both regions have upper surfaces which are co-planar. The co-planar surfaces, a departure from previous practice, make submicron lithography easier. The regions are annealed to form twin tubs.

Abstract: A method to achieve good stepper focus and exposure over an entire wafer for a particular mask level before the start of a product run is described. This method can also be used to produce a characterization of lens field curvature (i.e., a surface of optimum focus across the lens) and to characterize lens astigmatism, defocus sensitivity, relative resolution, and other characteristics, and to check the stepper for optical column tilt. The process prevents the complexities of resist development from affecting determination of focus. The process involves forming an array of latent images in a resist and examining the scattered light from the edges of the latent images. Analysis of the scattered light quickly provides information on correct exposure and focus together with lens characteristics over the printing field.

Abstract: A method of semiconductor fabrication which permits the creation of openings which have dimensions smaller than what may be achieved by conventional lithography. In an illustrative processing sequence, a pattern transfer material is deposited upon another material layer. The pattern transfer material is covered with photoresist which is subsequently patterned. With the patterned photoresist as a mask, the pattern transfer material is etched with a process which creates inward sloping walls. Then the pattern transfer material is used as a mask to etch the underlying material. The inward sloping walls of the pattern transfer material permit creation of an opening in the underlying material which is smaller than the corresponding opening in the photoresist. The method may also be used to create trenches or field oxides which have dimensions smaller than those achievable by lithography.

Abstract: A buck switching DC-to-DC regulator having a resistor and capacitor in combination across the storage inductor to measure output current and voltage. The resistor connects to the input of the inductor and the capacitor to the output of the inductor. The junction of the resistor and capacitor connects to an error amplifier for controlling the switching regulator. The regulator may be paralleled for more output current by connecting the outputs together and providing a common reference voltage to all the regulators.

Abstract: A logic gate arrangement having a master gate or section for controlling the logic threshold voltage of slave gates responsive to the master. Both the master and slave gates have two opposite conductivity type transistors disposed in combination with a logic function circuit. The transistors have a common gate connection to a control input. Varying the voltage on the control input varies the logic threshold voltage of the gate. The logic function in the master gate is typically an inverter, with input and output connected together and driving the control inputs of the slave gates. The logic function of the slave gates may be a variety of different logic functions. The logic threshold voltage of the slave gates is substantially the same as a voltage applied to the control input of the master gate.

Abstract: A high resolution high speed comparator featuring a differential amplifier that is coupled to two high amplification output stages. The output stages assist in rapidly amplifying input signals, yet do not interfere with comparator offset cancellation. In a preferred embodiment the comparator is made up of three stages, an input sampling network, a first amplifier stage, and a second amplifier stage, with the high amplification output stages being located in the first amplifier stage.

Abstract: A preamplifier overload control circuit which enhances the dynamic range of the preamplifier. Separate paths shunt corresponding DC and AC components of the signal from an electro-optical device away from the preamplifier input. The amount of shunting in both paths are controlled by a common control signal, here the average DC value of the signal, such that substantially all of the DC signal is shunted away from the preamplifier input.

Abstract: A method an apparatus for block or stream encrypting text uses an autokeyed rotational state vector to encrypt plain text to yield cipher text. The text is stored as a block in a buffer of an arbitrary number of bytes. Each byte of plain text in the buffer encrypted to yield a byte of cipher text by using a rotational state vector, and the rotational state vector is updated or changed as a function of one or more of: the cipher text, the plain text and a key. The encryption operation is advantageously a series of alternating non-linear and linear transformations. The method of encryption is advantageously involutory in that the encryption method and apparatus for a given key is identical to the decryption method and apparatus with the same key.

Abstract: A method of treating the surface of a metal nitride barrier layer on an integrated circuit to reduce the movement of silicon through the barrier. The metal nitride barrier (such as TiN) is exposed to a nitrogen plasma, thereby improving the barrier properties of the metal nitride barrier.

Abstract: An optical amplifier having high overall gain and low gain tilt, useful in an optical transmission system or the like. The amplifier has a doped optical fiber as the amplification medium and two pumps, the shorter wavelength one propagating with the signal being amplified and the longer wavelength one propagating opposite the signal being amplified. A wavelength selective reflective fiber grating is disposed along the doped fiber to reflect the second pump signal. The addition of the grating allows the amplifier to have a higher gain with a lower gain tilt than amplifiers without the grating. Positioning the grating along the fiber allows for the control of the overall gain with respect to the gain tilt for a given fiber length.

Abstract: Briefly, in accordance with one embodiment of the invention, a refined timing recovery circuit for retiming a recovered data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector.

Abstract: An integrated ringing signal detector sufficiently small for implementation on a single PCMCIA card. The detector has a DC-blocking capacitor 28 disposed between the telephone line and a bridge rectifier 27. The output 29 of the rectifier 27 connects to a voltage detector 23 which detects when the ringing signal exceeds a predetermined voltage. Output 30 of the voltage detector 23 triggers thyristor switch 24 into conduction. Switch 24 remains conductive until current flowing therein falls below the holding current of the thyristor switch 24. Current limiter 25 limits the current flowing therein to a substantially fixed predetermined amount of current, sufficient for the adequate operation of the LED in the opto-coupler transducer 22. The transducer 22 is shown here as an opto-coupler having an LED transmitter and a phototransistor receiver to provide galvanic (high-voltage) isolation between the telephone line and the utilization device, here a modem.

Abstract: A line driver having two halves arranged in a push-pull configuration. Each half has a pass transistor, connected between a power supply rail and an output terminal, and an amplifier with an output coupled to the output terminal. Only one of the pass transistors conducts at any given time. A sense transistor, coupled between the power supply rail and the input of the amplifier, varies the output of the amplifier to compensate for variations in the conductivity of the conducting pass transistor. Preferably, the current density in the sense transistor is substantially the same as in the conducting pass transistor.

Abstract: An overvoltage protection circuit using a diode bridge and a thyristor. The inputs to the bridge (first and second terminals) are coupled to a telephone line to be protected. The positive output of the bridge connects to a ground while the negative output of the bridge (intermediate node) connects through a thyristor to the ground. The thyristor is triggered into conduction when the voltage on the negative output of the bridge exceeds a reference voltage. The reference voltage is preferably the battery voltage for the telephone line.

Abstract: A unity gain or buffer amplifier having a low offset voltage. The amplifier uses two emitter followers of different conductivity types (PNP and NPN) in an up-down emitter or voltage follower configuration to provide high input impedance and low output impedance. By using both PNP and NPN transistors in a current mirror, the base-emitter voltages of the input and output transistors are forced to be substantially the same, reducing the offset voltage. N- and P-channel MOSFETs can be substituted for the NPN and PNP transistors. Single ended and push-pull arrangements are shown.

Abstract: A solid state circuit breaker which provides high voltage isolation between a control circuit and a power source is described. The circuit breaker comprises a receiver for providing a control signal in response to a transmitter that is electrically isolated from the receiver, a solid state switch that closes in response to the control signal thereby allowing a load current to flow through the switch, a current sensor for measuring the load current, and an inhibit circuit responsive to the current sensor for inhibiting the control signal when the load current exceeds a predetermined magnitude thereby opening the switch without adjusting the transmitter. After opening the switch, the inhibit circuit is responsive to the transmitter for allowing the control signal thereby closing the switch.

Abstract: High-efficiency clock generator circuits having single or complementary outputs for driving capacitive loads. The clock generator has therein at least one pair of complementary FET switches, coupled between the output of the generator and power supply rails, and an inductor. The generator is operated at a frequency approximately equal the resonant frequency of the inductor combined with the capacitance of the load. Energy normally stored in the load and dissipated in the FETs as in conventional clock generators is instead stored in the inductor and returned to the loads for reuse.